SoC Reset Isolation for Safety Island Hang Prevention
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Solution Overview
Problem
Functional safety systems for complex System on a Chip (SoC) require internal reset generation with redundancy to ensure high-level safety standards, but existing solutions increase system cost and may cause safety island hang during resets.
Innovation Solution
A fully integrated power on reset generation circuit with continuous voltage monitoring and redundant multi-stage sequencing, including internal oscillators, voltage detection stages, and a safety island to prevent hang conditions by managing pending transactions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage detectors and supervisory functions are implemented outside the SoC, then system cost increases, but functional safety requirements are met
Solution Approach 1:
The patent integrates voltage detectors, supervisory functions, and reset generation circuitry directly into the SoC device. This merging of previously external safety components with the core processor creates a unified integrated circuit that meets functional safety requirements (ISO 26262, IEC 61508) while reducing system cost and complexity by eliminating separate external safety ICs
Solution Approach 2:
The SoC is designed with multi-functional integrated circuitry that performs both core processing functions and safety-critical functions (voltage detection, supervision, reset generation) within the same device. This universal approach allows a single component to fulfill multiple roles, reducing the need for separate dedicated safety components
2Ease of operation
If the safety island is reset along with the non-safety portion of the SoC, then reset simplicity is maintained, but pending transactions are lost causing safety island hang
Solution Approach 1:
The patent divides the SoC into distinct segments: a safety island containing safety-critical functions and a non-safety portion containing other functions. This segmentation allows independent reset control where the non-safety portion can be reset without affecting the safety island, preventing transaction loss and hang conditions while maintaining operational reliability
Solution Approach 2:
The patent introduces reset management circuitry that acts as an intermediary between the reset signal and the safety island. This intermediary controls the timing and propagation of reset signals, ensuring that pending transactions are properly completed or aborted before the safety island is reset, thereby preventing hang conditions
3Reliability
If redundant multi-stage voltage monitoring is implemented, then functional safety redundancy is achieved, but device complexity increases
Solution Approach 1:
The patent combines multiple stages of voltage monitoring and supervisory functions into a single integrated circuit within the SoC. This merging approach achieves the required redundancy for functional safety while reducing overall device complexity by eliminating the need for multiple separate external monitoring components
Solution Approach 2:
The patent implements a nested structure where multiple levels of voltage monitoring are integrated within the SoC hierarchy. The monitoring circuitry is embedded within the device fabric, with voltage detection stages nested at different levels of the power distribution network, achieving comprehensive monitoring with compact integrated implementation
Data Source
AI summary
Disclosed embodiments include an electronic system with a power on reset (POR) circuit. The POR circuit includes first voltage detection circuitry to perform a first detection on a supply voltage and to output a first control signal in response to the first detection, second voltage detection circuitry to perform a second detection on the supply voltage and to output a second control signal in response to the second detection, and third voltage detection circuitry to perform a third detection on the supply voltage and to output at least one third control signal in response to the third detection. The POR circuit further has sequencing circuitry with a first input to receive the at least one third control signal and to output a reset signal in response to the at least one third control signal.