SoC XOR Compactor with Skewed Assignment for Fault Isolation
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Solution Overview
Problem
Existing top-level compactors for systems on a chip (SoC) with multiple identical cores face challenges in being X-tolerant and handling multiple identical faults, as symmetric assignment configurations can lead to X-states corruption and masking of faults due to identical core outputs.
Innovation Solution
The implementation of a compactor with XOR logic gates, where each input is associated with a distinct time delay or location, allowing for time-skewed or space-skewed assignment configurations to isolate and handle X-states and multiple identical faults effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If symmetric assignment configuration is used in the compactor, then X-states can be isolated to a specific XOR logic gate, but multiple identical faults are masked and cannot be detected
Solution Approach 1:
The patent applies asymmetry by introducing time-skewed or space-skewed assignment configurations that break the symmetry of the symmetric assignment. In time-skewed assignment, different time delays are applied to inputs of XOR gates, while in space-skewed assignment, different spatial positions are used. This asymmetry ensures that identical faults from multiple cores do not produce identical outputs that cancel each other out, thereby enabling fault detection while maintaining X-state isolation capabilities
Solution Approach 2:
The patent introduces dynamics by making the assignment configuration flexible and adaptable. The compactor can dynamically switch between symmetric, time-skewed, and space-skewed assignment configurations based on test requirements. This dynamic capability allows the system to optimize for either X-state isolation or fault detection depending on the specific testing scenario, resolving the contradiction between these two capabilities
2Productivity
If multiple cores are tested simultaneously, then test productivity increases, but a compactor is required to compact compressed responses which increases device complexity
Solution Approach 1:
The patent applies segmentation by dividing the compactor into multiple XOR logic gates, each handling specific inputs from cores. The compactor structure is segmented into parallel processing paths with distinct time delays or spatial positions. This segmentation allows simultaneous processing of responses from multiple cores while keeping each XOR gate relatively simple, thus enabling high test throughput without excessive complexity in individual components
Solution Approach 2:
The patent applies universality by designing the compactor XOR gates to perform multiple functions. Each XOR gate not only compactS responses but also provides X-state isolation and enables fault detection through the skewed assignment configuration. The same compactor structure serves multiple purposes: compacting data, isolating X-states, and detecting faults, thereby reducing the need for additional dedicated components and lowering overall device complexity
3Device complexity
If symmetric assignment is used, then the compactor structure is simple, but X-states corrupt known values reducing test coverage
Solution Approach 1:
The patent applies asymmetry by introducing time delays or spatial skew to the compactor configuration. This asymmetric configuration prevents X-states from corrupting all known values simultaneously, as the skew ensures that X-states from different cores affect different XOR gate outputs at different times or positions. This maintains test coverage while keeping the compactor configuration relatively simple and systematic
Data Source
AI summary
Systems disclosed herein provide for efficient top-level compactors for systems on a chip (SoCs) with multiple identical cores. Embodiments of the systems provide for compactors with a time-skewed assignment configuration, compactors with a space-skewed assignment configuration, compactors with time/space-skewed assignment configuration, and compactors that can selectively switch between the time/space-skewed assignment configuration and a symmetric assignment configuration.