Soft Erase State for Flash Memory Cell Reliability
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Solution Overview
Problem
The deterioration of memory cell arrays in semiconductor memory devices, particularly flash memory devices, increases with program/erase cycles, leading to reduced reliability and data integrity.
Innovation Solution
Implementing a method where memory cells are operated with a soft erase state and program states using a second reference voltage greater than the first, allowing for efficient programming and erasing while minimizing the number of erase pulses and reducing threshold voltage distribution changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional erase operations are performed to erase memory cells, then data can be erased, but the memory cell array deteriorates and reliability decreases with increased program/erase cycles
Solution Approach 1:
The patent applies parameter changes by introducing a soft erase state with a specific threshold voltage range (between first and second reference voltages) as an intermediate state between fully programmed and fully erased states. This allows the memory cells to be partially erased without completing the full erase cycle, thereby reducing wear on the memory cell array while still achieving data erasure when needed. The peripheral circuit controls the threshold voltage distribution to maintain cells in this soft erase state, extending the operational lifespan of the memory device.
2Reliability
If multiple erase pulses are applied to ensure complete erasure, then data erasure is achieved, but the number of erase pulses increases and memory cell wear accelerates
Solution Approach 1:
The patent applies partial action by implementing a soft erase state that performs partial erasure rather than complete erasure. The peripheral circuit maintains memory cells in this intermediate state where threshold voltages are between the first and second reference voltages, achieving sufficient data erasure for most applications without requiring multiple full erase pulses. This partial erasure approach reduces the total number of erase pulses needed while maintaining adequate data erasure completeness.
3Adaptability or versatility
If threshold voltage distribution is widely spread, then memory cells can store multiple bits, but the variation in threshold voltages increases and programming precision decreases
Solution Approach 1:
The patent applies local quality by creating a specific local state (soft erase state) with controlled threshold voltage characteristics. Instead of allowing uniform threshold voltage distribution across all memory cells, the peripheral circuit maintains a localized threshold voltage range between the first and second reference voltages for cells in the soft erase state. This localized control enables multi-bit storage capability while maintaining acceptable programming precision within this specific state, as the threshold voltage variation is confined to a controlled range rather than being widely distributed.
Data Source
AI summary
A method of operating a semiconductor memory device, given the case where memory cells have an erase state less than a first reference voltage and a plurality of program states greater than the first reference voltage, includes performing an erase operation so that the memory cells have a soft erase state less than a second reference voltage, and performing a program operation so that each of the memory cells has the soft erase state or one program state greater than the second reference voltage.