Soft-Error-Hardened Circuit Layout for Low-Overhead Logic Protection
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Solution Overview
Problem
Current radhard-by-design technologies for protecting logic circuits against soft errors, such as triplication and duplication methods, incur significant power and area overhead and are inefficient in handling multiple bit upsets (MBUs) or single event multiple upsets (SEMU) in logic circuits.
Innovation Solution
A layout methodology that generates specific circuit cells and arranges them to provide global soft-error protection by placing nodes with opposite effects close to each other and nodes with the same effect further apart, using techniques like the Dual Interlocked Cell (DICE) latch and redundant logic gates, to ensure that single events affect only one path, preventing errors from propagating.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If triplication or duplication methods are used to protect logic circuits against soft errors, then reliability is improved, but power consumption and area increase significantly
Solution Approach 1:
The circuit is divided into functional segments with dedicated error protection units. Each segment processes signals independently through separate paths, allowing error detection and correction without requiring full circuit triplication. This segmentation reduces the overall redundancy overhead while maintaining soft error protection capability.
Solution Approach 2:
Error protection units are introduced as intermediary components between functional circuit blocks. These units monitor and correct errors without requiring the main functional circuits to be replicated. The intermediaries handle the protective function separately, reducing the power and area overhead compared to full triplication of functional blocks.
2Reliability
If triplication or duplication methods are used to protect logic circuits against soft errors, then reliability is improved, but area overhead increases significantly
Solution Approach 1:
The circuit architecture is segmented into functional blocks with shared error protection resources. By dividing the circuit and allowing multiple blocks to share common protection units, the area required for error protection is significantly reduced compared to dedicating separate protection circuits to each functional block.
Solution Approach 2:
Error protection units are designed with multi-functional capability to serve multiple functional blocks. A single error protection unit can protect different circuit segments at different times, reducing the total area required for error protection infrastructure while maintaining comprehensive coverage across the entire circuit.
3Reliability
If traditional redundancy methods are used, then soft error protection is achieved, but the circuit cannot effectively handle multiple bit upsets or single event multiple upsets
Solution Approach 1:
Error protection units incorporate feedback mechanisms that monitor the state of protected signals and dynamically adjust correction strategies. When multiple bit upsets are detected, the feedback loop activates enhanced correction protocols that can recover from MBU and SEMU conditions, providing adaptability that traditional static redundancy methods lack.
Solution Approach 2:
The error protection system transitions from static redundancy to dynamic error handling. The protection units can adapt their operation mode based on the type and severity of errors detected, enabling effective handling of both single bit upsets and more complex multiple bit upset scenarios through dynamic response adjustment.
Data Source
AI summary
This invention comprises a layout method to effectively protect electronic circuits against soft errors (non-destructive errors) and circuit cells, which are protected against soft errors. The invention applies a layout method to sequential and combinational logic to generate specific circuit cells with netlists and layouts which are hardened against single event generated soft-errors. It also devices methods of how two or more such cells should be laid out and placed relative to each other, in order to have the best global soft-error protection.