Soft Post-Package Repair for Memory Devices
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Solution Overview
Problem
Current post-package repair methods for memory devices, such as blowing antifuses, introduce significant delays due to the time required for the process, which can negatively impact memory performance, especially when compared to other memory operations that occur in nanoseconds.
Innovation Solution
The implementation of a soft post-package repair method that utilizes volatile memory to store defective address data, allowing for rapid remapping of memory addresses without the need for persistent changes, thereby reducing the delay associated with traditional repair protocols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional post-package repair methods (blowing antifuses) are used, then defective memory cells can be repaired, but significant delays occur impacting memory performance
Solution Approach 1:
The patent creates a copy of the defective address data and stores it in volatile memory, allowing rapid remapping operations without modifying the original non-volatile storage. This copying approach enables fast repair operations while preserving the ability to maintain repair data across power cycles through the non-volatile memory backup.
Solution Approach 2:
The patent introduces volatile memory as an intermediary layer between the non-volatile memory (antifuse) and the memory controller. This intermediary enables rapid access and remapping operations by loading repair data into volatile memory, where it can be quickly processed without the delays associated with direct non-volatile memory operations.
2Ease of repair
If antifuse programming is performed for post package repair, then defective addresses can be remapped, but the process takes approximately 200 milliseconds which is much slower than nanosecond-scale memory operations
Solution Approach 1:
The patent performs preliminary action by pre-loading the defective address data from non-volatile memory into volatile memory during initialization or power-up. This preliminary loading ensures that when repair operations are needed, the data is already available in fast-access volatile memory, eliminating the need for slow non-volatile memory access during actual repair operations.
Solution Approach 2:
The patent implements a dynamic repair system where the remapping data can be loaded into volatile memory when needed and cleared or updated as required. This dynamic approach allows the system to switch between using volatile memory for fast operations and non-volatile memory for persistent storage, optimizing performance based on operational requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables memory device repair with a delay comparable to other memory operations, improving overall performance and yield while being compatible with existing protocols and programmable elements, and applicable to various memory devices like DRAMs and NAND flash memories.
Implementation Method 1
volatile memory configured to store defective address data responsive to entering a soft post-package repair mode
Implementation Method 2
a match logic circuit configured to generate a match signal indicating whether address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory
Implementation Method 3
a decoder configured to select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory
Data Source
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AI summary
Apparatus and methods for soft post package repair are disclosed. One such apparatus can include memory cells in a package, volatile memory configured to store defective address data responsive to entering a soft post-package repair mode, a match logic circuit and a decoder. The match logic circuit can generate a match signal indicating whether address data corresponding to an address to be accessed matches the defective address data stored in the volatile memory. The decoder can select a first group of the memory cells to be accessed instead of a second group of the memory cells responsive to the match signal indicating that the address data corresponding to the address to be accessed matches the defective address data stored in the volatile memory. The second group of the memory cells can correspond to a replacement address associated with other defective address data stored in non-volatile memory of the apparatus.