Software Cache Coherence Protocol with Load Balancer
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Solution Overview
Problem
Fixed hardware solutions for cache coherence in shared memory multiprocessor systems are inflexible and costly, limiting the effectiveness of cache coherence protocols.
Innovation Solution
A software-based cache coherence protocol is implemented using a processing unit with processor threads that execute memory requests and perform cache coherence operations based on trap signals and coherence information provided by the cache, with a load balancer distributing coherence requests across multiple threads to optimize performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed hardware state machines are used for cache coherence, then cache coherence operations can be performed reliably, but the system loses flexibility and incurs high costs due to dedicated hardware requirements
Solution Approach 1:
The patent replaces the mechanical hardware state machine system with a software-based coherence engine that runs on general-purpose processor threads. This substitution eliminates dedicated hardware while maintaining cache coherence functionality through software execution, thereby improving flexibility and reducing costs while preserving reliability through structured software protocols
2Reliability
If fixed hardware state machines are used for cache coherence, then cache coherence operations can be performed reliably, but the system incurs high costs due to dedicated hardware
Solution Approach 1:
The patent replaces expensive dedicated hardware state machines with software-based coherence engines executed on general-purpose processor threads. This eliminates the need for specialized hardware manufacturing, reducing system costs while maintaining reliability through well-structured software protocols that can be deployed on standard processors
Solution Approach 2:
The patent makes general-purpose processor threads perform cache coherence operations in addition to their normal computational tasks. By enabling processor threads to handle both application workloads and coherence management, the system eliminates dedicated hardware components, reducing manufacturing costs while maintaining reliable coherence operations through multi-functional software execution
3Adaptability or versatility
If software-based cache coherence is implemented, then system flexibility and cost are improved, but processing overhead may increase due to software execution
Solution Approach 1:
The patent implements a dynamic coherence engine that can adapt its operation mode based on system state. The coherence engine can be activated or deactivated dynamically, and can switch between different coherence protocols as needed. This dynamic approach allows the system to optimize between flexibility and processing throughput by enabling software-based coherence only when needed, rather than always incurring the overhead
Solution Approach 2:
The patent introduces a load balancer as an intermediary component that manages coherence requests and distributes them across multiple processor threads. This intermediary optimizes the workload distribution, preventing any single thread from becoming a bottleneck and minimizing the overall processing overhead while maintaining the flexibility benefits of software-based coherence
4Productivity
If multiple processor threads are used for cache coherence operations, then processing capacity is increased, but load balancing complexity increases
Solution Approach 1:
The patent segments coherence requests into different types and routes them to appropriate processor threads based on their characteristics. The load balancer divides the coherence workload into manageable segments and assigns them to available threads, reducing the complexity of managing multiple threads by organizing the workload systematically rather than handling all requests uniformly
Data Source
AI summary
Software-based cache coherence protocol. A processing unit may execute a memory request using a processor thread. In response to detecting a cache hit to shared or a cache miss associated with the memory request, a cache may provide both a trap signal and coherence information to the processor thread of the processing unit. After receiving the trap signal and the coherence information, the processor thread may perform a cache coherence operation for the memory request using at least the received coherence information. The processing unit may include a plurality of processor threads and a load balancer. The load balancer may receive coherence requests from one or more remote processing units and distribute the received coherence requests across the plurality of processor threads. The load balance may preferentially distribute the received coherence requests across the plurality of processor threads based on the operation state of the processor threads.