Software-Defined Testbench Processor for High-Bandwidth IC Testing
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Solution Overview
Problem
Existing solutions struggle to generate test signals efficiently for modern integrated circuits with high bandwidth, and new vulnerabilities like row-hammer require updated test patterns, which existing methods find difficult to accommodate without complex customization.
Innovation Solution
A software-defined testbench processor that generates customizable test streams using pipelined RTL blocks, ALU generators, and distributed instruction graphs, allowing for high throughput and easy extension to test various integrated circuit devices without requiring intricate customization of register transfer language (RTL) logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing test signal generation methods are used, then simple integrated circuits can be tested, but high-bandwidth integrated circuits cannot be sufficiently tested
Solution Approach 1:
The patent implements a software-defined testbench processor where test patterns are generated dynamically through programmable instruction sets rather than fixed hardware logic. This allows the test signal generation to adapt to different bandwidth requirements and circuit complexities by loading appropriate test algorithms into the processor's memory and executing them sequentially, thereby achieving both high throughput and flexibility.
Solution Approach 2:
The patent replaces traditional hardware-based finite state machines and combinatorial logic with a software-execution model on a programmable processor. Test patterns are generated by executing software instructions that manipulate test data through arithmetic logic units and memory structures, substituting mechanical hardware logic with software-based control flow to achieve higher adaptability and throughput.
2Reliability
If new test patterns are created to test new vulnerabilities, then testing coverage improves, but customization complexity increases
Solution Approach 1:
The patent creates a universal testbench processor architecture that can execute multiple different test patterns through a single programmable platform. The processor includes general-purpose arithmetic logic units, memory structures, and control logic that can be configured via software to implement various test algorithms including row-hammer tests, conventional memory tests, and custom vulnerability-specific patterns without requiring hardware redesign.
Solution Approach 2:
The patent enables easy creation of new test patterns by modifying software parameters and instruction sequences rather than changing hardware structure. Test characteristics such as pattern type, data width, access sequences, and vulnerability-specific parameters can be adjusted by loading different software configurations into the processor, allowing rapid adaptation to new vulnerabilities without RTL customization.
3Productivity
If software-defined testbench processor is implemented, then throughput and flexibility improve, but hardware resource requirements increase
Solution Approach 1:
The patent segments the testbench processor into modular functional units including separate arithmetic logic units, memory structures (instruction memory and data memory), control logic, and output interfaces. This segmentation allows efficient resource utilization by dedicating specific hardware blocks to specific functions while sharing common resources like buses and clocks, thereby achieving high throughput without proportionally increasing total hardware area.
Data Source
AI summary
Integrated circuit devices, systems, and circuitry are provided to perform signal tests on a device under test. One such integrated circuit device may include memory having instructions to generate a number of test streams to send to a device under test and a testbench processor. The testbench processor may generate the test streams based on the instructions using thread execution circuitry that switches context based on context identifiers corresponding to respective test streams.