Software Performance Profiling with Non-Unique Virtual Addresses

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Solution Overview

Problem

In processors with shared virtual address spaces, such as those used by MIPS Technologies, it is challenging to uniquely identify and profile the performance of individual application processes in user mode, as virtual addresses are not unique, making it difficult to measure software performance at a per-instruction level.

Innovation Solution

A system that includes a processor with a memory map specifying user and kernel mode regions, where a probe collects trace information and a host system processes this data using a profiling module that associates process names, PIDs, and instruction counters to identify performance issues, even when virtual addresses are not unique.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If virtual address translation with ASID is used to support multiple processes, then process isolation and memory management are improved, but virtual addresses are no longer unique across processes making performance profiling difficult

Engineering Contradiction:
Improveprocess isolationVSAvoidperformance profiling accuracy
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent introduces an intermediary mapping layer that translates non-unique virtual addresses into unique profiling identifiers. The system captures the virtual address and ASID combination, maps it to a unique process identifier through intermediary data structures (hash tables and mapping tables), and uses this intermediary representation for performance profiling. This allows the system to maintain process isolation through ASID while achieving unique address identification for profiling purposes.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If address sampling is used to profile performance, then measurement capability is improved, but the ability to uniquely identify processes is lost when virtual addresses are shared

Engineering Contradiction:
Improveperformance measurementVSAvoidprocess identification
Core Design Contradiction:
Measurement precisionVSLoss of information

Solution Approach 1:

The patent implements a nested data structure approach where multiple levels of identification are combined. The system nests the virtual address within the ASID context, and further nests both within process-specific data structures. The profiling data structure contains nested elements: virtual address samples are nested within ASID-specific buckets, which are nested within process identification layers, creating a hierarchical nesting that preserves process identification information while enabling performance measurement.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The patent adds another dimension to address identification by combining the virtual address (first dimension) with the ASID (second dimension) to create a composite unique identifier. This dimensional expansion transforms the problematic single-dimension virtual address into a multi-dimensional identification space where the combination of address and ASID provides unique process-level identification, enabling both measurement and process identification simultaneously.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS8185717B2Apparatus and method for profiling software performance on a processor with non-unique virtual addresses
Publication Date: 2012.05.22 ARM FINANCE OVERSEAS LTD
  • US8185717B2 patent drawing
  • US8185717B2 patent drawing
  • US8185717B2 patent drawing

AI summary

A system includes a processor with a memory map specifying a user mode region with virtual address translation by a memory management unit and a kernel mode region with direct virtual address translation. The processor executes an application in the user mode region where virtual addresses are not unique. A probe receives trace information from the processor. A host system receives the trace information from the probe. The host system includes a data structure associating a process name, a process identification and a set of instruction counters. Each instruction counter is incremented upon the processing of a designated virtual address within the trace information. A profiling module processes information associated with the process name and set of instruction counters to identify a performance problem in the application.