Software-Based Test Pattern Generation for High-Speed ATE
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Solution Overview
Problem
Conventional Automated Test Equipment (ATE) systems, particularly those using Field-Programmable Gate Arrays (FPGAs), struggle to keep up with the increasing data rates and implement main bus protocols like PCIe Generation 5 and CXL, making them inadequate for testing high-capacity and high-bandwidth devices such as modern SSDs.
Innovation Solution
The use of high-performance CPUs, specifically High Core Count (HCC) processors, to generate and apply test patterns directly to devices under test (DUTs) via software, leveraging direct memory access (DMA) and supporting PCIe protocols, allowing for scalable and flexible testing without the limitations of hardware-based designs like ASICs or FPGAs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If FPGAs are used to generate test patterns in conventional ATE systems, then design flexibility and time to market are improved, but the system cannot keep up with increasing data rates and cannot implement main bus protocols like PCIe Generation 5 and CXL
Solution Approach 1:
The patent replaces the hardware-based FPGA system with a software-based CPU system. Specifically, it uses a host processor with CPU cores to generate test patterns through software algorithms instead of hardware logic, and uses a PCIe interface controller to handle high-speed data transfer. This substitution allows the system to achieve PCIe Generation 5 and CXL protocol compliance while maintaining design flexibility through software programmability.
2Productivity
If hardware-based APG is used to generate test patterns, then data can be generated at maximum speed of the DUT, but the tester becomes the bottleneck for high-capacity and high-bandwidth devices
Solution Approach 1:
The patent changes the fundamental parameters of the test pattern generation system by moving from hardware-based to software-based generation. It utilizes the host processor's CPU cores and memory subsystem to generate test patterns at speeds that match high-capacity and high-bandwidth devices. The system uses DMA (Direct Memory Access) to transfer test patterns between the host processor memory and the device under test, eliminating the tester bottleneck while maintaining high productivity.
3Speed
If specialized bus interfaces are used in DUTs, then interface performance is optimized, but conversion electronics are required which add complexity
Solution Approach 1:
The patent implements a universal testing interface based on PCIe technology that can directly interface with various DUTs without requiring specialized conversion electronics. The host processor system uses a PCIe interface controller that can handle multiple protocols and device types through software configuration, eliminating the need for dedicated conversion circuits while maintaining high interface performance. This universal approach reduces system complexity while preserving speed.
Data Source
AI summary
A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs) and a hardware interface module coupled to the test computer system and controlled by the test computer system, the hardware interface module operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs. The hardware interface module includes a memory for storing instructions and data, a high performance processor coupled to the memory, the high performance processor operable to perform testing functionality at high speed for application of test signals to the plurality of DUTs, the high performance processor operable to perform the testing functionality under control of instructions and data from the memory and under control from software commands from the test computer system, wherein further the high performance processor is not natively capable of low power mode operation. The test system also includes a low power module coupled to and external to the high performance processor, the low power module capable of operating in at least one low power mode, the high performance processor for directing the low power module to configure the plurality of DUTs into at least one low power mode and further for testing the plurality of DUTs using commands and data in low power. The test system further includes driver hardware for applying the commands and data in low power to the plurality of DUTs which are configured for low power operation during the testing.