SOI Substrate Boundary Shape for Leakage Reduction
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Solution Overview
Problem
In semiconductor devices, particularly those with sub-40 nm feature sizes, it is challenging to simultaneously enhance performance by improving operation speed and reducing power consumption due to increased leakage current and variability in transistor characteristics, which complicates voltage margin management and integration scaling.
Innovation Solution
The technique involves modifying the shape of the boundary portion of the SOI layer and shallow trench isolation on an SOI substrate by recessing the SOI edge more than the shallow trench isolation edge, ensuring a curved surface at the silicon substrate corner, which helps maintain uniform electrical flux density and reduces power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If transistor feature size is miniaturized to sub-40 nm, then operation speed and power consumption per transistor are improved, but leakage current increases and velocity saturation occurs
Solution Approach 1:
The patent applies different materials to different regions of the transistor structure. Specifically, high-k dielectric material is used in the gate insulating film region to reduce leakage current, while strained silicon is used in the channel region to maintain carrier mobility and prevent velocity saturation. This local differentiation of material properties resolves the contradiction between reducing power consumption and suppressing leakage current at sub-40 nm dimensions.
Solution Approach 2:
The patent employs composite material structures combining multiple materials with complementary properties. The gate insulating film consists of a stack including high-k dielectric layers and silicon oxide layers, creating a composite structure that provides both low leakage current and appropriate electrical characteristics. The channel region combines strained silicon with specific crystal orientations to achieve both high mobility and reduced short-channel effects, resolving the power consumption versus leakage current contradiction.
2Productivity
If transistor feature size is miniaturized, then more transistors can be integrated on a chip, but variability in characteristics among transistors increases
Solution Approach 1:
The patent systematically optimizes multiple parameters simultaneously to maintain characteristic uniformity during miniaturization. This includes adjusting the thickness of the gate insulating film and BOX layer, controlling the strain level in the silicon channel, and optimizing the doping concentration in source/drain regions. By coordinating changes in these parameters, the patent achieves both high integration density and reduced characteristic variability among transistors.
Solution Approach 2:
The patent divides the transistor structure into functionally optimized segments: the gate insulating film is segmented into multiple layers with different materials (high-k dielectric and silicon oxide), and the channel is segmented with specific strain configurations. This segmentation allows each region to be independently optimized, reducing the impact of process variations and improving characteristic uniformity across the chip while maintaining high integration density.
3Speed
If gate insulating film is thinned to improve operation speed, then switching performance increases, but tunneling current increases and power consumption increases
Solution Approach 1:
The patent uses a composite gate insulating film structure combining high-k dielectric material with silicon oxide layers. The high-k material provides high dielectric constant to maintain strong electric field for fast switching, while the silicon oxide layers provide low leakage properties. This composite structure enables thin film thickness for high-speed operation while suppressing tunneling current through the high-k material's superior leakage resistance compared to conventional silicon oxide alone.
Solution Approach 2:
The patent applies high-k dielectric material specifically in the gate insulating film region where both high-speed switching and low leakage are critical, while using conventional silicon oxide in other regions where different properties are needed. This localized application of high-k material resolves the contradiction between thinning the gate insulating film for speed and preventing tunneling current.
Data Source
AI summary
A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.