SOI Cavity Layout for High-Q GaN Passive Components
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Solution Overview
Problem
GaN on Si technology requires thinner substrates to dissipate heat effectively, leading to lower quality factors in passive components and limited impedance in transmission lines, which restricts current-carrying capability and increases system losses.
Innovation Solution
The use of a silicon-on-insulator (SOI) substrate configuration with cavities and conductor-less regions to reduce parasitic capacitances and electro-migration effects, enhancing the quality factor and impedance of inductors and transmission lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the substrate thickness is reduced to dissipate heat effectively, then heat dissipation performance is improved, but the quality factor of passive components deteriorates
Solution Approach 1:
The patent introduces cavities extending into the substrate from the rear surface, creating a three-dimensional structure that reduces parasitic capacitance without requiring thinner substrates. This dimensional approach allows heat dissipation improvement while maintaining component quality factor by separating the thermal management function from the electrical performance constraint.
Solution Approach 2:
The substrate is segmented by introducing cavities that divide the continuous substrate material into regions separated by air gaps or low-dielectric-constant material. This segmentation reduces the effective parasitic capacitance between conductive features and the substrate, thereby improving the quality factor while maintaining adequate substrate thickness for heat dissipation.
2Temperature
If the substrate thickness is reduced to dissipate heat effectively, then heat dissipation performance is improved, but the impedance of transmission lines deteriorates
Solution Approach 1:
By creating cavities that extend vertically into the substrate, the patent modifies the electromagnetic field distribution in three dimensions. This reduces the parasitic capacitance between transmission lines and the substrate, thereby increasing the characteristic impedance without requiring substrate thinning, while still maintaining adequate thickness for heat dissipation.
3Object-affected harmful factors
If transmission line traces are narrowed to achieve desired impedance, then impedance is improved, but current-carrying capability deteriorates
Solution Approach 1:
The patent extracts the parasitic capacitance component by introducing cavities between the transmission lines and the substrate. This removal of harmful capacitive coupling allows wider trace widths to be used while maintaining the desired characteristic impedance, thereby improving current-carrying capability without sacrificing impedance control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The SOI substrate configuration with cavities and conductor-less regions improves the quality factor and impedance of inductors and transmission lines, reducing system losses and increasing the current-carrying capability of GaN on Si devices.
Implementation Method 1
The cavity 160 may be used to reduce parasitic capacitances within the substrate
Implementation Method 2
SOI substrate can realize additional benefits such as eliminating substrate leakage, reducing cross talk between circuit components
Data Source
AI summary
A semiconductor device and method of manufacture is presented. A silicon-on-insulator (SOI) substrate includes a layer of gallium nitride on a first surface of the SOI substrate. A device is formed over the first surface of the substrate and a first conductive feature is formed over the first surface of the substrate and electrically coupling the first conductive feature to the device. A first cavity is formed in a second surface of the SOI substrate directly below the first conductive feature, wherein the first cavity includes first upper cavity surface defined by a surface of a layer of silicon dioxide in the SOI substrate.