SOI Device Charging Protection via Bulk Contacts
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Solution Overview
Problem
SOI devices face issues with undesirable charge accumulation during manufacturing and operation, which affects transistor characteristics and can be exacerbated by plasma-based etching processes, leading to parasitic capacitances and radiation-induced charge carrier generation.
Innovation Solution
The implementation of an SOI semiconductor device with conductive bulk substrate contacts extending through the active and buried insulation layers, providing conductive paths to drain charges from the gate electrode and body of the transistor, thereby reducing antenna charging and protecting against charge damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If plasma-based etching processes are used to manufacture SOI devices, then manufacturing precision and device performance are improved, but undesirable charge damage accumulates in the gate insulation layer and transistor components
Solution Approach 1:
A conductive layer is introduced as an intermediary between the gate insulation layer and the gate electrode. This conductive layer acts as a mediator that captures and drains away charge accumulation caused by plasma-based etching processes, preventing charge damage to the gate insulation layer while allowing the etching process to continue with high precision.
Solution Approach 2:
The harmful charge accumulation is extracted from the gate structure by providing dedicated conductive paths through bulk substrate contacts. These contacts extend through the active layer and buried insulation layer to the bulk substrate, actively removing charge from vulnerable components during and after plasma-based etching processes.
2Productivity
If critical feature sizes are reduced to increase package density and improve signal performance, then chip area and signal propagation delay are reduced, but parasitic capacitances in bulk silicon substrates increase
Solution Approach 1:
The active transistor layer is extracted from the bulk silicon substrate and placed on an insulating layer, forming a silicon-on-insulator structure. This separation removes the source of parasitic capacitances from the active device region, allowing critical feature sizes to be reduced for higher density without suffering from bulk substrate parasitic effects.
Solution Approach 2:
A buried insulation layer is introduced as an intermediary between the active silicon layer and the bulk substrate. This insulating mediator electrically isolates the active region from the bulk substrate, preventing parasitic capacitance formation while allowing the device to benefit from reduced feature sizes for improved density and performance.
3Reliability
If the active region volume is reduced to improve high-frequency performance and reduce radiation effects, then parasitic capacitances are reduced, but charge accumulation below the channel region more adversely affects transistor characteristics
Solution Approach 1:
A conductive layer is introduced as an intermediary between the gate insulation layer and gate electrode, while bulk substrate contacts provide additional conductive pathways. These intermediary conductive structures capture and drain charge accumulation that would otherwise affect the transistor channel region, protecting the reduced-volume active region from charge-related degradation.
Solution Approach 2:
Charge accumulation below the channel region is actively extracted through bulk substrate contacts that extend through the active layer and buried insulation layer to the bulk substrate. This extraction mechanism removes harmful charges from the vicinity of the channel, allowing the active region to maintain small dimensions for high-frequency performance without suffering from charge accumulation effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces undesirable charge accumulation, improving transistor performance and reliability by isolating conductive paths for the gate and source regions, thereby minimizing parasitic capacitances and radiation-induced effects.
Implementation Method 1
a first conductive bulk substrate contact extending through the active layer and the buried insulation layer, the first conductive bulk substrate contact being conductively coupled to the source region and the bulk substrate, and a second conductive bulk substrate contact extending through the active layer and the buried insulation layer, the second conductive bulk substrate being conductively coupled to the gate electrode and the bulk substrate
Data Source
AI summary
The present invention is directed to an SOI device with charging protection and methods of making same. In one illustrative embodiment, a device is formed on an SOI substrate including a bulk substrate, a buried insulation layer and an active layer. The device includes a transistor formed in an isolated portion of the active layer, the transistor including a gate electrode and a source region. The device further includes a first conductive bulk substrate contact extending through the active layer and the buried insulation layer, the first conductive bulk substrate contact being conductively coupled to the source region and the bulk substrate, and a second conductive bulk substrate contact extending through the active layer and the buried insulation layer, the second conductive bulk substrate being conductively coupled to the gate electrode and the bulk substrate.