SOI Semiconductor Device With Intermediate N-Type Region
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Solution Overview
Problem
Current semiconductor devices with thick film SOI substrates face challenges in maintaining high withstand voltage while minimizing the layer thickness of the semiconductor layer, as decreasing impurity concentration in the drift region leads to increased depletion layer extension and capacitance reduction, making it difficult to manufacture deep trenches and achieve desired voltage levels.
Innovation Solution
Incorporating a first conductive type region with a higher impurity concentration than the semiconductor layer but lower than the drain region, positioned deeper than the drain region, to suppress depletion layer extension towards the drain, allowing for a thinner semiconductor layer without compromising withstand voltage, thereby simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the impurity concentration of the drift region is decreased to increase withstand voltage, then the withstand voltage increases, but the depletion layer extends greatly toward the drain region and the depletion layer capacitance decreases, requiring the SOI layer to be made large in layer thickness
Solution Approach 1:
The patent introduces an N-type region with intermediate impurity concentration (1×10^16/cm³ to 1×10^18/cm³) within the drift region, creating a localized zone with different electrical properties. This N-type region has higher impurity concentration than the surrounding drift region but lower than the drain region, forming a gradient structure that locally modifies the electric field distribution and suppresses depletion layer extension toward the drain, thereby maintaining high withstand voltage with thinner SOI layers
Solution Approach 2:
The patent changes the impurity concentration parameter by introducing an N-type region with intermediate concentration between the low-concentration drift region and high-concentration drain region. This parameter gradient (from 3.5×10^14/cm³ in drift region to 1×10^16-1×10^18/cm³ in N-type region to 1×10^19/cm³ in drain region) modifies the electrical characteristics, suppressing depletion layer extension and enabling thinner SOI layers while maintaining 600V withstand voltage
2Ease of manufacture
If the layer thickness of the SOI layer is increased to facilitate deep trench formation, then deep trenches can be formed more easily, but the manufacturing complexity and time increase
Solution Approach 1:
The patent changes the impurity concentration parameter to create an N-type region with intermediate concentration, which modifies the material properties to enable easier deep trench formation in thinner SOI layers (30 μm or less), thereby reducing manufacturing time and complexity while maintaining ease of trench formation
3Reliability
If the layer thickness of the BOX layer is increased to increase drain voltage apportionment, then the withstand voltage is maintained, but the SOI layer cannot be made thin due to manufacturing limitations
Solution Approach 1:
The patent introduces a localized N-type region with intermediate impurity concentration within the drift region, creating a specific zone with modified electrical properties. This local modification suppresses depletion layer extension toward the drain and enables thinner SOI layers to achieve high withstand voltage, independent of BOX layer thickness
Solution Approach 2:
The patent changes the impurity concentration parameter by introducing an N-type region with intermediate concentration (1×10^16/cm³ to 1×10^18/cm³), which modifies the electrical characteristics to enable thinner SOI layers to achieve high withstand voltage without relying on increased BOX layer thickness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the semiconductor device to achieve a withstand voltage of at least 600V with a thinner SOI layer, reducing manufacturing complexity and time by allowing for easier formation of deep trenches, while maintaining the required voltage levels.
Implementation Method 1
an N-type region 15 having an N-type impurity concentration higher than the N-type impurity concentration of the drift region 11 and lower than the N-type impurity concentration of the drain region 14 is formed in the drift region 11. With the N-type region 15, extension of a depletion layer toward the drain region 14 can be suppressed
Data Source
AI summary
A semiconductor device according to the present invention includes: an insulating layer; a semiconductor layer of a first conductive type laminated on the insulating layer; an annular deep trench having a thickness reaching the insulating layer from a top surface of the semiconductor layer; a body region of a second conductive type formed across an entire thickness of the semiconductor layer along a side surface of the deep trench in an element forming region surrounded by the deep trench; a drift region of the first conductive type constituted of a remainder region besides the body region in the element forming region; a source region of the first conductive type formed in a top layer portion of the body region; a drain region of the first conductive type formed in a top layer portion of the drift region; and a first conductive type region formed in the drift region, having a deepest portion reaching a position deeper than the drain region, and having a first conductive type impurity concentration higher than the first conductive type impurity concentration of the semiconductor layer and lower than the first conductive type impurity concentration of the drain region.