SOI Device ESD Enhancement Circuit with Clamping Diodes
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Solution Overview
Problem
High voltage Silicon-On-Insulator (SOI) devices experience unstable electrostatic discharge (ESD) robustness due to uncontrollable SOI substrate bias during ESD events, limiting their performance and flexibility.
Innovation Solution
An ESD enhancement circuit is integrated within the SOI device, comprising a pair of clamping diodes connected back to back, with cathodes connected to terminals and anodes directly connected to the SOI substrate, allowing the substrate to be clamped to a lower potential, thereby controlling the bias and enhancing ESD performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the SOI substrate is directly connected to circuit ground, then the ESD robustness is improved, but the flexibility of the SOI device is limited
Solution Approach 1:
The ESD protection function is segmented from the main SOI device circuitry. The ESD enhancement circuit is implemented as a separate integrated circuit that interfaces with the SOI device, allowing independent optimization of ESD protection without constraining the main device flexibility. This segmentation enables the SOI device to maintain full operational flexibility while receiving dedicated ESD protection from the separate circuit.
Solution Approach 2:
The ESD enhancement circuit acts as an intermediary between the ESD threat and the SOI device. It includes intermediate components such as clamping diodes and protection transistors that mediate the ESD current path, protecting the SOI device without requiring direct ground connection that would limit flexibility. The intermediary circuit provides the necessary protection while maintaining signal integrity and device adaptability.
2Adaptability or versatility
If the SOI substrate bias is left floating, then the device flexibility is maintained, but the ESD robustness becomes unstable
Solution Approach 1:
The ESD enhancement circuit dynamically adjusts the SOI substrate bias based on operating conditions. The circuit includes voltage-dependent components such as diodes and transistors that automatically modulate the substrate bias voltage to optimize ESD protection while maintaining device flexibility. This dynamic control allows the system to adapt to different operating states without compromising either flexibility or ESD robustness.
Solution Approach 2:
The circuit changes the substrate bias parameter dynamically to achieve stable ESD robustness. By actively controlling the substrate bias voltage through the ESD enhancement circuit, the system can adjust this critical parameter to maintain optimal ESD protection characteristics while preserving device flexibility. The parameter change is controlled and reversible, unlike a fixed ground connection.
3Reliability
If an ESD enhancement circuit is integrated within the SOI device, then the ESD robustness is improved, but the device complexity increases
Solution Approach 1:
The ESD enhancement circuit is merged with the SOI device into a single integrated package. The protection circuit shares common substrates, interconnect structures, and manufacturing processes with the main SOI device, reducing overall system complexity despite adding ESD protection functionality. This merging approach allows the ESD circuit to be fabricated using the same CMOS process, minimizing additional complexity.
Solution Approach 2:
The ESD enhancement circuit is designed with universal components that serve multiple functions. The clamping diodes and protection transistors not only provide ESD protection but also contribute to normal device operation and signal routing. This multi-functionality reduces the need for dedicated ESD-only components, thereby minimizing the increase in overall device complexity while achieving robust ESD protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution achieves stable high breakdown voltage and safe operation area for SOI devices by controlling the SOI substrate bias during ESD events, improving the flexibility and reliability of high voltage SOI devices.
Implementation Method 1
Electrostatic discharge (ESD) is a sudden release of electrostatic charge which can result in high electric fields and currents within an integrated circuit
Implementation Method 2
The ESD enhancement circuit comprises a pair of clamping diodes. The pair of clamping diodes is connected back to back: having cathodes respectively connected to two terminals of the SOI device and anodes directly connected together and directly connected to the SOI substrate
Data Source
AI summary
The present disclosure relates to an integrated circuit. The integrated circuit comprises a silicon on insulator (SOI) device separated from a SOI substrate by an insulation layer. The SOI device comprises a power supply terminal, a ground terminal, a first I/O terminal and a second I/O terminal. An electrostatic discharge (ESD) protection circuit is integrated with the SOI device. The ESD protection circuit is configured to shunt current between two terminals of the SOI device during an ESD surge event. An electrostatic discharge (ESD) enhancement circuit is integrated with the SOI device. The ESD enhancement circuit is configured to clamping the SOI substrate to a lower potential of the two terminals of the SOI device.