SOI Subjacent ESD Protection Transistor for Density
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Solution Overview
Problem
Integrated circuits produced using FDSOI technology face challenges in achieving distinct threshold voltages for transistors due to zero doping in the channel, and existing solutions for ESD protection are not efficient in terms of integration density and discharge current diversion.
Innovation Solution
The use of isolation trenches of reduced depth and dimensions, along with a biased ground plane and implanted areas, forms an ESD protection device that allows for significant discharge current diversion without compromising integration density, and modulates threshold voltages by adjusting the doping of the ground planes and their bias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If isolation trenches of reduced depth and dimensions are used for ESD protection, then integration density is maintained, but discharge current diversion capability is compromised
Solution Approach 1:
The protection transistor is nested beneath the active transistor, with the protection transistor's source region formed in the first well and its drain region in the second well, both located under the active transistor's channel. This nesting allows the protection device to occupy the same lateral footprint as the active device, maintaining integration density while providing ESD protection through the subjacent transistor structure.
Solution Approach 2:
The invention moves the protection transistor from a lateral arrangement to a vertical/subjacent arrangement. The protection transistor is positioned in the depth dimension beneath the active transistor, utilizing the vertical space in the SOI structure. This dimensional transition allows ESD protection functionality without increasing the lateral area occupied by protection structures.
2Adaptability or versatility
If different gate materials are used to achieve distinct threshold voltages, then transistor threshold voltage differentiation is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The invention applies local quality by creating differently doped ground planes (first ground plane with first doping concentration, second ground plane with second doping concentration) beneath specific regions of the transistor channel. This localized doping variation allows different threshold voltages in different lateral regions of the same transistor, enabling multi-threshold functionality without requiring different gate materials across the wafer.
Solution Approach 2:
The invention changes the doping concentration parameter of the ground planes to achieve threshold voltage differentiation. By varying the doping concentration in different ground plane regions (first doping concentration vs. second doping concentration), the invention creates transistors with distinct threshold voltages using the same gate material, thus avoiding the manufacturing complexity of integrating multiple gate materials.
3Adaptability or versatility
If channel doping is increased to raise threshold voltage, then transistor threshold voltage increases, but switching speed decreases
Solution Approach 1:
The invention segments the threshold voltage control by creating multiple independently doped ground plane regions (first ground plane region, second ground plane region) beneath different portions of the channel. This segmentation allows different threshold voltages to be established in different channel regions, enabling the circuit to have both fast-switching transistors (with lower threshold voltage) and low-power transistors (with higher threshold voltage) on the same integrated circuit without compromising overall performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables the production of integrated circuits with distinct threshold voltages and effective ESD protection, ensuring reliable operation and reduced integration density impact, while allowing for efficient diversion of electrostatic discharge currents.
Implementation Method 1
By altering the doping of the ground planes and their bias, it is possible to define a range of threshold voltages for the different transistors
Implementation Method 2
By altering the doping of the ground planes and their bias, it is possible to define a range of threshold voltages for the different transistors
Implementation Method 3
the transistors are generally surrounded by isolation trenches (designated by the acronym STI for 'Shallow Trench Isolation') which extend into the wells
Implementation Method 4
integrated circuits such as these also include devices for protection against accidental electrostatic discharges (ESD) that might impair these transistors
Data Source
AI summary
An integrated circuit features a FET, an UTBOX layer plumb with the FET, an underlayer ground plane with first doping plumb with the FET's gate and channel, first and second underlayer semiconducting elements, both plumb with the drain or source, electrodes in contact respectively with the ground plane and with the first element, one having first doping and being connected to a first voltage, the other having the first doping and connected to a second bias voltage different from the first, a semiconducting well having the second doping and plumb with the first ground plane and both elements, a first trench isolating the first FET from other components of the integrated circuit and extending through the layer into the well, and second and third trenches isolating the FET from the electrodes, and extending to a depth less than a plane/well interface.