SOI Die Excavated Substrate Support for Singulation Stability
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Solution Overview
Problem
Semiconductor-on-insulator (SOI) devices are susceptible to stress and defects during singulation due to their thin active layer, leading to potential plastic deformation, wafer warpage, and electrical performance degradation.
Innovation Solution
The implementation of an excavated substrate region and a support region, optionally combined with a strengthening layer, provides stabilizing force to the SOI die during singulation, enhancing structural support and thermal dissipation while preserving electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the active layer is made thin to achieve electrical isolation in SOI devices, then electrical isolation performance is improved, but structural stability during singulation deteriorates
Solution Approach 1:
The substrate is segmented into an excavated region and a support region, creating a framework structure that provides mechanical strength while allowing the active layer to remain thin for electrical isolation. The support region forms a grid-like pattern that distributes stress during singulation.
Solution Approach 2:
Different regions of the substrate are given different properties: the excavated region removes material to reduce stress and improve thermal dissipation, while the support region retains material to provide mechanical strength. This local differentiation resolves the contradiction between thin active layer requirements and structural stability.
2Strength
If additional support structures are added to stabilize the SOI die during singulation, then structural stability is improved, but device complexity increases
Solution Approach 1:
The support function is merged into the substrate itself through the framework structure, eliminating the need for separate support structures like handle wafers. The substrate simultaneously provides mechanical support, thermal dissipation, and structural stability during singulation.
Solution Approach 2:
The substrate serves its own support function through the framework structure, eliminating the need for external support structures. The excavated and support regions work together to provide self-stabilization during processing.
3Temperature
If the substrate is removed to improve thermal dissipation, then thermal management is improved, but structural support capability deteriorates
Solution Approach 1:
The substrate is segmented into excavated regions for thermal dissipation and support regions for structural strength. This segmentation allows simultaneous optimization of both thermal management and mechanical support capabilities.
Solution Approach 2:
Different regions of the substrate are optimized for different functions: excavated regions provide thermal dissipation pathways while support regions maintain structural integrity. This local quality differentiation resolves the contradiction between thermal management and structural support.
Data Source
AI summary
Embodiments of the present invention provide for the provisioning of efficient support to semiconductor-on-insulator (SOI) structures. Embodiments of the present invention may additionally provide for SOI structures with improved heat dissipation performance while preserving the beneficial electrical device characteristics that accompany SOI architectures. In one embodiment, an integrated circuit is disclosed. The integrated circuit comprises a silicon-on-insulator die from a silicon-on-insulator wafer. The silicon on insulator die comprises an active layer, an insulator layer, a substrate, and a strengthening layer. The substrate consists of an excavated substrate region, and a support region, the support region is in contact with the insulator layer. The support region and the strengthening layer are configured to act in combination to provide a majority of a required stabilizing force to the silicon-on-insulator die when it is singulated from the silicon-on-insulator wafer.


