SOI FET Source/Drain Geometry for Low Capacitance Current Boost
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Solution Overview
Problem
In semiconductor-on-insulator FETs, the increased resistance of ultra-thin semiconductor layers necessitates raised source/drain regions to boost saturation current, but this results in increased overlap capacitance, degrading performance.
Innovation Solution
The design includes source/drain regions with a unique shape, featuring a wider first portion in the insulator layer and a narrower second portion in the semiconductor layer, reducing the distance to the channel region without increasing spacer thickness, and optionally using stress-inducing semiconductor materials to enhance charge carrier mobility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If raised source/drain regions are used to boost saturation current, then saturation current is improved, but overlap capacitance increases
Solution Approach 1:
The source/drain regions are configured with different widths at different depths: a first width at a first depth and a second width at a second depth. This three-dimensional configuration allows the source/drain regions to provide sufficient current drive while reducing the lateral overlap with the gate, thereby minimizing capacitance.
Solution Approach 2:
The source/drain regions exhibit varying cross-sectional dimensions at different depths, creating localized properties optimized for different functions: wider portions for current conduction and narrower portions for reduced capacitive coupling with the gate structure.
2Productivity
If distance between source/drain regions and channel region is reduced, then saturation current is boosted, but overlap capacitance increases
Solution Approach 1:
By utilizing the vertical dimension with different depths and widths, the source/drain regions can be positioned closer to the channel region to enhance current drive while the varying cross-sectional dimensions ensure that the lateral overlap with the gate remains minimized, thus reducing capacitance.
Solution Approach 2:
The cross-sectional dimensions of the source/drain regions are varied at different depths, allowing optimization of both the distance to the channel region and the overlap with the gate structure. This parameter variation enables simultaneous improvement of saturation current and reduction of overlap capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration boosts saturation current while minimizing overlap capacitance, thereby improving performance without compromising capacitance.
Implementation Method 1
each source/drain region can include multiple semiconductor layers including one that is grown laterally from the semiconductor layer during processing and that is specifically a stress-inducing semiconductor material for improving charge carrier mobility in the channel region
Data Source
AI summary
Disclosed are a semiconductor structure and method of forming the structure. The structure includes a field effect transistor (FET) with a channel region between source/drain regions that extend through a semiconductor layer and into an insulator layer, that include a first portion in the insulator layer, and a second portion on the first portion in the semiconductor layer and, optionally, extending above the semiconductor layer. The first portion is relatively wide, includes a shallow section below the second portion, and a deep section adjacent to the channel region and overlayed by the semiconductor layer. The uniquely shaped first portion boosts saturation current to be boosted to allow the height of the second portion to be reduced to minimize overlap capacitance. Optionally, each source/drain region includes multiple semiconductor materials including a stress-inducing semiconductor material grown laterally from the semiconductor layer to improve charge carrier mobility in the channel region.