SOI FinFET Channel Width and Switching Speed via Dynamic Back Bias
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Solution Overview
Problem
Current transistor designs, particularly in FINFETs, face challenges in increasing effective channel width without increasing fin width, which limits current capacity and switching speed.
Innovation Solution
The implementation of a fully depleted semiconductor-on-insulator (SOI) FINFET structure with non-quantized width fins and dynamic back bias control through a buried oxide layer, allowing for increased effective channel width and improved current capacity without additional masks or process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If fin width is increased to increase effective channel width, then current capacity is improved, but device area and manufacturing complexity increase
Solution Approach 1:
The patent extends the channel region vertically by forming fins that protrude from the semiconductor substrate surface. The gate wraps around these fins to control current flow through the vertical channel, effectively increasing the channel width without proportionally increasing the planar device footprint. This dimensional transition from 2D to 3D architecture resolves the contradiction between current capacity and device area.
Solution Approach 2:
The gate structure is formed to wrap around and enclose the fin structures on multiple sides, creating a nested configuration where the gate contains the channel region. This nested arrangement maximizes the effective channel width within a compact footprint, as the gate controls current through vertical channels formed by the fins while occupying minimal lateral space.
2Productivity
If fin width is increased to increase effective channel width, then current capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The channel region is segmented into multiple discrete fin structures that protrude from the substrate. Each fin acts as an independent current channel controlled by the gate, allowing the effective channel width to be increased by adding more fins or increasing fin height rather than simply expanding the lateral dimensions. This segmentation enables scalable current capacity with controlled manufacturing complexity.
3Speed
If effective channel width is increased to improve switching speed, then switching speed is improved, but fin width must be increased which limits design flexibility
Solution Approach 1:
The patent implements dynamic back bias control by applying adjustable voltages to the substrate or buried oxide layer. This dynamically modulates the threshold voltage of the FinFET, enabling adaptive control of switching characteristics. The dynamic biasing mechanism provides design flexibility to optimize switching speed for different operating conditions without requiring physical changes to the fin dimensions, thus resolving the contradiction between switching speed and design flexibility.
Data Source
AI summary
A transistor includes at least one fin structure (e.g., three fin structures) and a gate. The fin structure is disposed above a semiconductor layer above an insulator layer of a semiconductor on insulator substrate. The gate is disposed over at least three sides of the fin structure and a portion of the semiconductor layer. A channel for the transistor is disposed in fin structure and the portion under the gate.