SOI Structure Reducing Harmonics via Local Doping
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Solution Overview
Problem
Conventional silicon-on-insulator (SOI) substrates used in RF switches often generate second and third order harmonics beyond the FCC limits due to fixed charges in the insulator layer or at the interface between the insulator and silicon substrate, leading to impedance variations with input signals.
Innovation Solution
A silicon-on-insulator structure with a semiconductor substrate having a first portion adjacent to the insulator layer doped with a specific concentration of a dopant and a second portion above it doped with a higher concentration of the same or different dopant, optionally including micro-cavities to balance conductivity and resistivity, which raises the threshold voltage of parasitic capacitors and reduces harmonic behavior.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional SOI substrate is used in RF switches, then the structure provides advantages such as reduced parasitic capacitances and elimination of latch-up, but fixed charges in the insulator layer or at the interface generate second and third order harmonics beyond FCC limits
Solution Approach 1:
The patent applies local quality by creating a dual-concentration doped region within the semiconductor substrate. The first concentration is present throughout the substrate, while a second, higher concentration is localized in a specific region adjacent to the insulator layer. This localized doping modification targets the specific problem area (interface region) without altering the entire substrate, thereby suppressing parasitic inversion charge formation at the critical interface while maintaining overall substrate properties.
Solution Approach 2:
The patent changes the dopant concentration parameter within the semiconductor substrate to resolve the harmonic generation issue. By introducing a second, higher concentration of dopant in the region adjacent to the insulator layer, the electrical characteristics of that specific region are modified. This parameter change increases the doping level locally to prevent inversion charge formation, thereby reducing harmonic generation while maintaining the beneficial properties of the SOI structure.
2Ease of manufacture
If fixed charges are present in the insulator layer or at the interface, then the SOI structure can be formed with standard processing, but inversion charge forms at the top surface of the silicon substrate leading to impedance variations and harmonic generation
Solution Approach 1:
The patent applies preliminary action by pre-doping the semiconductor substrate with a second, higher concentration of dopant in the region adjacent to the insulator layer before the insulator layer is formed. This preliminary doping action ensures that when the insulator layer is subsequently deposited, the underlying semiconductor region is already prepared with the appropriate electrical characteristics to prevent inversion charge formation, thereby maintaining impedance control throughout the manufacturing process.
3Object-generated harmful factors
If the dopant concentration is increased in the second portion to suppress parasitic inversion charge, then harmonic generation is reduced, but the conductivity of the substrate increases which may affect device performance
Solution Approach 1:
The patent resolves this contradiction by applying local quality - the higher second concentration of dopant is confined to a specific region adjacent to the insulator layer, while other regions of the substrate maintain the lower first concentration. This spatial differentiation allows the substrate to have high doping (low conductivity) where needed to suppress parasitic effects, while maintaining appropriate conductivity in other regions for device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The structure effectively suppresses the formation of parasitic inversion charge layers, thereby reducing harmonic generation within the specified limits, while maintaining high resistivity and minimizing additional manufacturing costs.
Implementation Method 1
The first portion can comprise, in a first concentration, a dopant having the given conductivity type. The second portion can comprise, in a second concentration that is greater than the first concentration, any of the following: the same dopant as in the first portion, a different dopant than that in the first portion but with the same conductivity type, or a combination thereof.
Implementation Method 2
the second portion can also comprise a plurality of micro-cavities so as to balance out, within the second portion, a dopant induced increase in conductivity with a corresponding micro-cavity induced increase in resistivity
Data Source
AI summary
Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.