SOI Embedded Memory Layout for Isolated Logic Processing
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Solution Overview
Problem
Existing methods for forming non-volatile memory devices alongside core logic devices on a composite substrate face challenges due to incompatible gate structure advances, where processing steps for memory cells adversely affect logic devices and vice versa, especially in silicon on insulator (SOI) substrates.
Innovation Solution
A method involving the formation of polysilicon layers and selective etching to create stack structures on an SOI substrate, allowing for the formation of non-volatile memory cells in one area and logic devices in another without interfering processes, using protective layers to safeguard the logic areas during memory cell formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If processing steps for memory cells are performed on a composite substrate with logic devices, then memory cells can be formed, but the processing steps adversely affect the logic devices
Solution Approach 1:
The substrate is divided into distinct memory cell regions and logic device regions, allowing independent processing of each region. Memory cell processing steps are applied only to memory regions while logic devices remain protected in their own regions, eliminating cross-contamination and adverse effects between the two device types.
Solution Approach 2:
The conflicting processing steps are extracted and applied selectively only to memory cell regions. By removing the insulating layer and forming memory structures in designated areas while leaving logic device areas untouched, the harmful effects are eliminated while still achieving memory cell formation.
2Reliability
If gate structure advances are implemented, then memory device performance improves, but compatibility with conventional composite structure methods is lost
Solution Approach 1:
Advanced gate structures are implemented locally in memory cell regions with specialized processing, while logic device regions maintain conventional structures. This allows each region to have optimized properties for its specific function without requiring universal process changes across the entire substrate.
Solution Approach 2:
The manufacturing process is made dynamic and adaptive, allowing different processing sequences and techniques to be applied to different regions of the substrate. The process flow can be adjusted to accommodate both advanced memory structures and conventional logic devices on the same chip.
3Manufacturing precision
If the insulating layer is removed from the entire substrate, then memory cells can be formed with deeper source and drain regions, but logic devices are adversely affected
Solution Approach 1:
The insulating layer removal is segmented to affect only memory cell regions. By applying the removal process selectively to memory areas while preserving the insulating layer in logic device areas, deeper source and drain regions are achieved in memory cells without compromising logic device integrity.
Solution Approach 2:
The substrate is prepared with region-specific characteristics before final device formation. Memory regions are pre-configured with removed insulating layers to enable deep diffusions, while logic regions maintain their insulating layers for protection, allowing both device types to be formed with their respective optimal structures.
Data Source
Figure 1
Figure 2A~2B
Figure 2C~2D
AI summary
A method of forming a semiconductor device where memory cells and some logic devices are formed on bulk silicon while other logic devices are formed on a thin silicon layer over insulation over the bulk silicon of the same substrate. The memory cell stacks, select gate poly, and source regions for the memory devices are formed in the memory area before the logic devices are formed in the logic areas. The various oxide, nitride and poly layers used to form the gate stacks in the memory area are formed in the logic areas as well. Only after the memory cell stacks and select gate poly are formed, and the memory area protected by one or more protective layers, are the oxide, nitride and poly layers used to form the memory cell stacks removed from the logic areas, and the logic devices are then formed.