SOI MOS Transistor Parameter Extraction via Back-Gate Capacitance
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Solution Overview
Problem
Current methods for extracting EOT and Weff parameters from MOS stacks on SOI substrates are unreliable and difficult to reproduce, especially due to challenges in accessing the flat band voltage and accurately determining capacitance characteristics, which hinders reliable comparison and adjustment of transistor performance.
Innovation Solution
A method involving the measurement of capacitance between the front and rear face gates of a MOS transistor on an SOI substrate, applying varying voltages to determine the flat band voltage and extracting EOT and Weff parameters by adjusting the measured characteristics to a theoretical model, specifically focusing on the depletion mode range to ensure accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional capacitance measurement methods are used on SOI substrates, then measurement simplicity is maintained, but measurement precision and reliability deteriorate due to inability to access flat band voltage
Solution Approach 1:
The measurement method is segmented into multiple distinct steps: applying specific voltage conditions to induce channel depletion, measuring capacitance under these controlled conditions, and processing the data to extract parameters. This segmentation allows each step to be optimized independently, improving overall measurement precision while managing complexity through systematic organization.
Solution Approach 2:
The method applies preliminary voltage conditions to the transistor before measurement to ensure the channel is in depletion mode. This preliminary action prepares the device in a known state that enables accurate access to flat band voltage and subsequent parameter extraction, resolving the issue of unreliable measurements on SOI substrates.
2Reliability
If voltage range is extended to access flat band voltage on SOI substrates, then parameter extraction reliability improves, but measurement complexity increases
Solution Approach 1:
The measurement method dynamically adjusts voltage conditions during the measurement process. By applying varying voltage levels to transition the channel between different operational states (particularly ensuring depletion mode), the method reliably accesses flat band voltage while providing a structured procedure that manages operational complexity.
Solution Approach 2:
The method incorporates feedback mechanisms where capacitance measurements under controlled voltage conditions are used to determine whether the channel is properly in depletion mode. This feedback ensures reliable parameter extraction by confirming the correct operational state is achieved, while the systematic nature of the feedback loop maintains procedural clarity.
3Measurement precision
If channel depletion mode is enforced for accurate parameter extraction, then EOT and Weff determination accuracy improves, but measurement conditions become more restrictive
Solution Approach 1:
The measurement method applies local quality control by specifically targeting the depletion mode condition for the channel during measurement. By enforcing this particular operational state locally during the measurement process, the method achieves high accuracy for EOT and Weff parameter extraction. The method remains adaptable to different transistor types and substrate conditions while maintaining this focused measurement approach.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for reliable and reproducible extraction of EOT and Weff parameters, enabling precise monitoring and adjustment of MOS transistor performance, even on SOI substrates where traditional methods fail, by accessing a broader range of voltage values and channel depletion conditions.
Implementation Method 1
measuring the electric current Ig(t) coming from the rear face gate as a function of Vgs and determining from this measurement the capacitance Cgb between the front face gate and the rear face of the transistor substrate
Data Source
Figure 1a~1b
Figure 2a~2b
Figure 3a~3b
AI summary
The invention relates to a method for measuring a set of parameters of a MOS transistor on a solid-state substrate, said set of parameters including at least the flat band voltage at the back face of the buried oxide, said method comprising the following steps: - applying to the back face of the transistor substrate a DC main voltage Vbs and an AC voltage v(t); - measuring the electric current lg(t) from the front-face gate and determining the capacitance Cbg between the back face of the transistor substrate and the front-face gate; - determining the set of parameters by fitting the characteristic Cbg(Vgb) to a theoretical model describing the behavior of a MOS transistor on a solid substrate, said set of parameters being able to include the effective work output of the gate metal Weff and the equivalent oxide thickness EOT.