SOI MOSFET Single Backgate Contact for Threshold Voltage Adjustment
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Solution Overview
Problem
Existing semiconductor devices face challenges in adjusting threshold voltages of pMOSFET and nMOSFET separately while maintaining high integration levels, as different backgate contacts are required for each, leading to increased footprint and reduced integration capabilities.
Innovation Solution
A semiconductor structure and manufacturing method involving an SOI substrate with a buried semiconductor layer doped with a first polarity, and a counter-doped region of opposite polarity self-aligned with the gate stack, allowing for adjustment of threshold voltages using a single backgate contact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate backgate contacts are provided for pMOSFET and nMOSFET to adjust threshold voltages independently, then threshold voltage adjustment capability is improved, but device footprint increases
Solution Approach 1:
The patent merges the backgate contacts of pMOSFET and nMOSFET into a single shared backgate contact structure. The buried semiconductor layer serves as a common backgate for both transistor types, allowing independent threshold voltage control through a single contact, thereby reducing device footprint while maintaining adaptability
Solution Approach 2:
The buried semiconductor layer is designed to serve multiple functions: it acts as a backgate for both pMOSFET and nMOSFET simultaneously, and the counter-doped region provides additional functionality for independent threshold voltage control. This multi-functional design eliminates the need for separate backgate contacts
2Length of moving object
If gate length is reduced below 45 nm to improve device scaling, then device density is improved, but short channel effects become more significant
Solution Approach 1:
The patent applies preliminary anti-action by introducing a buried semiconductor layer with counter-doped region before the short channel effects can degrade device performance. This structure pre-establishes an electric field configuration that counteracts the harmful short channel effects, allowing continued scaling below 45 nm while maintaining reliability
Solution Approach 2:
The patent changes the electrical parameters of the device by introducing a buried semiconductor layer with specific counter-doping. This modifies the electric field distribution and potential profile in the channel region, effectively suppressing short channel effects and enabling further gate length reduction
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables independent adjustment of threshold voltages for pMOSFET and nMOSFET using a single backgate contact, thereby improving the integration level of semiconductor devices.
Implementation Method 1
The additional semiconductor layer is ion doped to form a backgate structure, to which a bias voltage is applied so as to adjust the threshold voltage of the semiconductor device
Implementation Method 2
implanting a dopant of a second polarity from the opening to form a counter-doped region in the backgate region
Data Source
AI summary
The present application discloses a semiconductor structure and method for manufacturing the same. The semiconductor structure comprises: an SOI substrate and a MOSFET formed on the SOI substrate, wherein the SOI substrate comprises, in a top-down fashion, an SOI layer, a first buried insulator layer, a buried semiconductor layer, a second buried insulator layer, and a semiconductor substrate, the buried semiconductor layer including a backgate region including a portion of the buried semiconductor layer doped with a dopant of a first polarity; the MOSFET comprises a gate stack and source/drain regions, the gate stack being formed on the SOI layer, and the source/drain regions being formed in the SOI layer at opposite sides of the gate stack; and the backgate region includes a counter-doped region, the counter-doped region is self-aligned with the gate stack and includes a dopant of a second polarity, and the second polarity is opposite to the first polarity. The embodiment of the present disclosure can be used for adjusting a threshold voltage of a MOSFET.