SOI Wafer Nitride Diffusion Barrier for Copper Contamination
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Solution Overview
Problem
Current buried SOI wafers with a diffusion barrier face challenges in preventing copper and mobile ion diffusion, leading to device degradation due to the use of copper and mobile ions like sodium or potassium during packaging and chip use, especially with thinner wafers and higher aspect ratio Through Silicon Via (TSV) structures.
Innovation Solution
The integration of a nitride layer as a diffusion barrier between the handle substrate and the oxide layers in the SOI wafer structure, combined with a bonding process that includes ion implantation and annealing, effectively prevents copper and mobile ion diffusion by forming a stable bonding interface and separation layer, thereby enhancing the quality of the silicon layer and reducing contamination risks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a buried oxide layer is used in SOI wafers, then device isolation and electrical performance are improved, but copper and mobile ions can diffuse through the oxide to reach devices causing threshold voltage shifts and degradation
Solution Approach 1:
A nitride layer is introduced as an intermediary diffusion barrier between the copper-containing structures and the buried oxide layer. The nitride layer has low copper solubility and acts as a mediator to block copper diffusion pathways, while also preventing mobile ion migration through the oxide, thus protecting the devices without altering the fundamental SOI structure
Solution Approach 2:
The patent creates a composite barrier structure combining nitride and oxide layers. The nitride layer is formed between the active semiconductor layer and the buried oxide, creating a multi-layer composite structure that leverages the low copper solubility of nitride and the electrical isolation properties of oxide to provide comprehensive protection against both copper diffusion and mobile ion contamination
2Productivity
If thinner silicon wafers are used, then device scaling and integration density are improved, but copper diffusion paths become shorter and contamination risks increase
Solution Approach 1:
The diffusion barrier is segmented into multiple distinct layers: a nitride layer positioned between the active semiconductor layer and the buried oxide, and potentially additional nitride layers at other strategic locations. This segmentation creates multiple discrete barriers that collectively block copper diffusion pathways more effectively than a single continuous barrier, addressing the increased contamination risk in thinned wafers
3Adaptability or versatility
If higher aspect ratio TSV structures are used, then via density and interconnect capability are improved, but copper diffusion through the via walls becomes more pronounced
Solution Approach 1:
The nitride diffusion barrier is applied locally at critical interfaces where copper diffusion is most likely to occur, specifically between the active semiconductor layer and the buried oxide. This local application of the barrier provides targeted protection at the most vulnerable diffusion pathways without requiring complete encapsulation of all copper structures, thus maintaining interconnect capability while preventing diffusion
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a high-quality SOI wafer with an embedded diffusion barrier that effectively prevents copper and mobile ion diffusion, improving the stability and performance of semiconductor devices by reducing threshold voltage shifts and device degradation.
Implementation Method 1
one of the first wafer and the second wafer includes a nitride layer... effectively prevents copper and mobile ion diffusion
Implementation Method 2
a bonding process that includes ion implantation and annealing
Implementation Method 3
a bonding process that includes ion implantation and annealing
Data Source
AI summary
An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor substrate and a second oxide layer, the first oxide layer being bonded to the second oxide layer, and one of the first wafer and the second wafer includes a nitride layer. The nitride layer can be formed between the semiconductor substrate and the second oxide layer. A third oxide layer can be formed on the semiconductor substrate and the nitride layer is formed between the second oxide layer and the third oxide layer. The nitride layer can be formed between the active semiconductor layer and the first oxide layer. The first wafer can include a third oxide layer formed on the active semiconductor layer and the nitride layer is formed between the third oxide layer and the first oxide layer.