Nitrogen Gradient Buried Oxide for SOI Boron Migration
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Solution Overview
Problem
Boron migration and segregation into buried oxide layers in semiconductor-on-insulator (SOI) structures lead to parasitic resistance and performance degradation in CMOS devices, particularly in ultra-thin SOI devices, where the presence of a buried oxide interface exacerbates these issues, and existing solutions like laser or flash anneal processes complicate device integration and design.
Innovation Solution
Incorporating a nitrogen gradient into the buried oxide layer of SOI structures to inhibit boron migration and segregation, using thermal and plasma nitriding methods to create tailored nitrogen profiles that peak at interfaces with the semiconductor layers, resulting in abrupt interfaces and low interfacial roughness, thereby blocking dopant migration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional spike anneal process is used for boron activation, then boron activation is achieved, but boron migration and segregation into the buried oxide layer occur, causing parasitic resistance and device performance degradation
Solution Approach 1:
A nitrogen-rich interface layer is introduced between the semiconductor layer and the buried oxide layer to act as a diffusion barrier. This intermediary layer prevents boron atoms from migrating into the buried oxide while allowing the spike anneal process to effectively activate boron dopants in the extension regions, thus resolving the contradiction between achieving boron activation and preventing boron loss.
Solution Approach 2:
The nitrogen-rich interface layer is formed in advance before the spike anneal process to preemptively block boron migration pathways. By establishing this protective barrier beforehand, the patent prevents the harmful boron-segregation effect from occurring during subsequent high-temperature processing steps, thereby maintaining device performance.
2Reliability
If laser or flash anneal processes are used for boron activation, then boron activation is achieved, but process flow flexibility is severely restricted and device integration complexity increases
Solution Approach 1:
The patent modifies the thermal processing parameters by using a conventional spike anneal process with optimized temperature and time parameters (e.g., 900-1100°C for 1-10 seconds) instead of requiring laser or flash anneal equipment. This parameter optimization allows standard semiconductor manufacturing equipment to achieve effective boron activation while maintaining process flexibility and reducing integration complexity.
3Power
If the buried oxide layer is made thinner to improve device performance, then drive current increases, but boron migration effects become more extreme and parasitic resistance increases
Solution Approach 1:
The nitrogen-rich interface layer serves as a diffusion barrier that decouples the relationship between buried oxide thickness and boron migration. This intermediary structure allows the use of thinner buried oxide layers to improve drive current while the nitrogen barrier prevents boron from migrating into the oxide, thus resolving the contradiction between achieving high drive current and preventing parasitic resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The nitrogen gradient effectively prevents boron migration and segregation, reducing parasitic resistance and enhancing device performance by maintaining dopant concentration, leading to improved MOSFET drive current and circuit performance.
Implementation Method 1
Incorporating a nitrogen gradient into the buried oxide layer of SOI structures to inhibit boron migration and segregation
Implementation Method 2
using thermal and plasma nitriding methods to create tailored nitrogen profiles that peak at interfaces with the semiconductor layers
Data Source
AI summary
A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.