SOI SRAM Cell Leakage Reduction via Dynamic Threshold Control
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Solution Overview
Problem
Reducing power consumption in SRAM circuits while maintaining operating stability and speed is challenging due to increased leakage currents and the need for symmetrical memory cell configurations, which are compromised by existing techniques that either increase transistor count or asymmetry.
Innovation Solution
The use of SOI transistors with a BOX layer to adjust threshold voltage and well layer potentials, reducing leakage currents and maintaining performance without increasing memory cell area or transistor count, by employing a configuration with common well layers electrically isolated from each other.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If power supply voltage is reduced to reduce power consumption, then power consumption decreases, but operating margins of transistors decrease leading to unstable operation
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the threshold voltage of transistors based on operational state. During read operations, threshold voltage is optimized for low leakage current, while during write operations, it is adjusted for high-speed operation. This dynamic parameter adjustment allows the circuit to maintain stability at reduced power supply voltages while achieving lower power consumption.
2Speed
If threshold voltage is reduced to maintain operating current level at lower power supply voltage, then operating speed is maintained, but leakage current increases resulting in increased power consumption
Solution Approach 1:
The patent implements dynamics by making the threshold voltage adjustable and time-dependent rather than fixed. The threshold voltage is dynamically changed based on whether the memory cell is performing read or write operations. During read operations, a higher threshold voltage is used to minimize leakage current, while during write operations, a lower threshold voltage is applied to ensure fast switching and maintain operating speed.
3Reliability
If transistors with different gate widths are used to improve read/write stability, then operational stability increases, but memory cell area increases
Solution Approach 1:
The patent applies asymmetry in the circuit configuration by using different transistor types (n-channel and p-channel) with optimized characteristics for their specific roles. Rather than using symmetric transistors with identical gate widths, the design exploits the inherent asymmetry between nMOS and pMOS devices to achieve stable read and write operations while maintaining a compact memory cell area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances operating speed and stability of SRAM circuits while reducing power consumption and leakage currents, maintaining performance and symmetry in memory cell design.
Implementation Method 1
a transistor including an SOI layer whose channel portion is insulated from a substrate portion by a BOX layer made up of an insulation layer
Data Source
AI summary
An object of the present invention is to provide a technique of reducing the power consumption of an entire low power consumption SRAM LSI circuit employing scaled-down transistors and of increasing the stability of read and write operations on the memory cells by reducing the subthreshold leakage current and the leakage current flowing from the drain electrode to the substrate electrode.Another object of the present invention is to provide a technique of preventing an increase in the number of transistors in a memory cell and thereby preventing an increase in the cell area.Still another object of the present invention is to provide a technique of ensuring stable operation of an SRAM memory cell made up of SOI or FD-SOI transistors having a BOX layer by controlling the potentials of the wells under the BOX layers of the drive transistors.