SOI Substrate with Localized Trap Rich Layer Resistivity
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Solution Overview
Problem
The integration of RFSOI substrates with trap rich layers, beneficial for RF applications, is incompatible with FDSOI technology's back polarization requirements, as the highly resistive trap rich layer hinders conduction necessary for controlling FDSOI transistors, and localized shaping of the trap rich layer during substrate fabrication is industrially infeasible.
Innovation Solution
A semiconductor on insulator substrate with a trap rich layer comprising polycrystalline semiconducting material or phase change material, featuring distinct regions with varying recrystallization states to adjust resistivity locally, allowing compatibility with both FDSOI and RFSOI technologies by creating regions suitable for each type of component, enabling back polarization of FDSOI components and reducing parasite conduction in RFSOI regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a highly resistive trap rich layer is formed to reduce parasite conduction for RF applications, then RF performance is improved, but back polarization capability for FDSOI transistors deteriorates
Solution Approach 1:
The trap rich layer is formed with spatially varying properties: regions with high trap density and high resistivity for RF components, and regions with lower trap density and lower resistivity for FDSOI components requiring back polarization. This local differentiation allows each region to optimize for its specific function while sharing the same substrate.
Solution Approach 2:
The substrate is divided into distinct functional zones: RFSOI regions with trap rich layers for RF/passive components, and FDSOI regions without trap rich layers or with modified trap rich layers for digital transistors requiring back gate control. This segmentation resolves the contradiction by providing specialized structures for each application type.
2Reliability
If a uniform trap rich layer is formed across the entire substrate, then RF and passive component performance is improved, but compatibility with FDSOI technology deteriorates
Solution Approach 1:
The trap rich layer properties are locally adjusted across the substrate: present and highly resistive in regions dedicated to RF/passive components, absent or modified in regions dedicated to FDSOI digital components. This enables the substrate to support multiple technology types simultaneously.
Solution Approach 2:
The substrate is designed as a universal platform that can accommodate both RFSOI and FDSOI technologies by implementing spatially selective trap rich layer formation, allowing a single substrate type to serve multiple functional purposes.
3Object-generated harmful factors
If the trap rich layer is made highly resistive to eliminate parasite conduction, then RF signal quality is improved, but conduction for back gate control deteriorates
Solution Approach 1:
The trap rich layer exhibits spatially differentiated electrical properties: high resistivity in RF regions to suppress parasite conduction, and low resistivity in FDSOI regions to enable efficient back gate control. This local quality variation resolves the contradiction between suppressing harmful conduction and enabling necessary conduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of a single substrate that can support both high-performance FDSOI and RF components by locally adjusting the trap rich layer's properties, reducing parasite currents and maintaining thermal stability, thus addressing the incompatibility issues between RFSOI and FDSOI technologies.
Implementation Method 1
a trap rich layer just underneath the BOX to capture free charges and thus considerably reduce or even eliminate formation of the parasite conducting layer
Implementation Method 2
good thermal stability at high temperature (up to about 1100° C.) compatible with the use of a CMOS process
Implementation Method 3
inserting a thin dielectric layer between the trap rich layer and the support layer to prevent or delay untimely recrystallization of the trap rich layer
Data Source
AI summary
A semiconductor on insulator type substrate, comprising at least:a support layer;a semiconductor surface layer;a buried dielectric layer located between the support layer and the semiconductor surface layer;a trap rich layer located between the buried dielectric layer and the support layer, and comprising at least one polycrystalline semiconductor material and/or a phase change material;in which the trap rich layer comprises at least one first region and at least one second region adjacent to each other in the plane of the trap rich layer, the material of the at least one first region being in an at least partially recrystallized state and having an electrical resistivity less than that of the material in the at least one second region.