SOI Semiconductor Layer Thickness Zoning for Mixed-Device Integration
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Solution Overview
Problem
Integrating different types of semiconductor devices with varying signal processing functions onto a single semiconductor-on-insulator (SOI) substrate is challenging due to the need for different semiconductor layer thicknesses, as logic devices require thin layers for low leakage and high switching speeds, RF switching devices need moderate layers for low capacitance, and power/I/O devices benefit from thick layers for threshold voltage control.
Innovation Solution
An integrated chip (IC) with an SOI substrate featuring a semiconductor layer of varying thicknesses in different regions, allowing for the integration of logic, RF switching, and power/I/O devices on a single substrate, where the semiconductor layer thickness is tailored to meet the specific performance requirements of each device type.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a uniform thin semiconductor layer is used across the entire SOI substrate, then logic devices achieve low leakage and high switching speeds, but power/I/O devices suffer from poor threshold voltage control
Solution Approach 1:
The patent implements a semiconductor layer with spatially varying thickness: thin regions (e.g., 50-150 nm) for logic devices to achieve low leakage and high switching speeds, and thick regions (e.g., 200-500 nm) for power/I/O devices to ensure proper threshold voltage control. This local differentiation resolves the contradiction by optimizing each device type for its specific performance requirements rather than using a uniform thickness across the entire substrate.
2Reliability
If a uniform thick semiconductor layer is used across the entire SOI substrate, then power/I/O devices achieve good threshold voltage control, but logic devices experience high leakage and reduced switching speeds
Solution Approach 1:
The patent creates distinct thickness zones within the semiconductor layer: thick regions providing adequate threshold voltage control for power/I/O devices, and thin regions enabling low leakage and high switching speeds for logic devices. This local quality approach allows simultaneous optimization of conflicting performance parameters in different spatial locations on the same substrate.
3Reliability
If different SOI substrates with different semiconductor layer thicknesses are used for different device types, then each device type achieves optimal performance, but device complexity and integration difficulty increase
Solution Approach 1:
The patent merges multiple thickness-optimized semiconductor layers into a single integrated structure with continuously varying or stepped thickness profiles. This consolidation allows logic devices, RF switching devices, and power/I/O devices to coexist on one substrate, each benefiting from locally optimized thickness while avoiding the complexity of assembling and bonding multiple separate substrates.
Solution Approach 2:
By implementing local thickness variation within a single substrate, the patent achieves device-specific optimization without requiring multiple substrates. The semiconductor layer transitions from thin regions for high-speed logic to thick regions for power devices, maintaining integration simplicity while delivering optimal performance for each device type.
4Ease of manufacture
If a single semiconductor layer thickness is used for all devices, then manufacturing is simplified, but no device can achieve optimal performance for its specific function
Solution Approach 1:
The patent implements a semiconductor layer with spatially varying thickness that can be formed using standard semiconductor manufacturing techniques such as selective epitaxial growth, selective chemical vapor deposition, or etch-back processes. This approach maintains relative manufacturing simplicity while enabling locally optimized thickness for different device functions, achieving a balance between ease of manufacture and device performance.
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip comprises a semiconductor substrate. A semiconductor layer is disposed over the semiconductor substrate. An insulating structure is buried between the semiconductor substrate and the semiconductor layer. The insulating structure has a first region and a second region. The insulating structure has a first thickness in the first region of the insulating structure, and the insulating structure has a second thickness different than the first thickness in the second region of the insulating structure.