SOI Transistors With Vertical Strain Source/Drain Structures
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Solution Overview
Problem
SOI-MOSFET devices face limitations in enhancing device performance due to the inability to effectively introduce strain materials in the thin source/drain regions, which restricts further improvement in device speed and performance.
Innovation Solution
A method is introduced to form transistors on SOI substrates by creating strain regions of increased volume in the source/drain structures through a process involving the formation of openings in the substrate, followed by the growth of strained materials using in-situ doped epitaxial growth, and subsequent annealing, allowing for enhanced strain introduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the silicon layer is made thin to achieve better short channel effects, then short channel effects are improved, but the ability to introduce strain materials in the source/drain regions is lost
Solution Approach 1:
The patent extends the source/drain structures vertically into the substrate beneath the thin silicon layer, creating a three-dimensional configuration. This allows strain materials to be introduced in the vertical dimension (into the substrate) while maintaining the thin horizontal silicon layer configuration needed for good short channel effects.
Solution Approach 2:
The strain-containing source/drain structures are nested within openings that extend through the thin silicon layer into the substrate. The strain materials are positioned within these openings, effectively nesting the strain introduction mechanism within the existing thin-film transistor structure without disrupting the thin silicon layer.
2Speed
If strain materials are introduced in source/drain regions to improve device performance, then device speed is improved, but the thin silicon layer configuration prevents effective strain material introduction
Solution Approach 1:
Instead of attempting to introduce strain materials laterally within the constrained thin silicon layer plane, the patent utilizes the vertical dimension by extending source/drain structures into the substrate. This provides adequate volume for strain material incorporation while maintaining compatibility with the thin silicon layer configuration.
Solution Approach 2:
The patent forms openings in the substrate and prepares the structure for strain material deposition before finalizing the source/drain regions. This preliminary preparation of the substrate openings enables subsequent strain material introduction without disrupting the already-formed thin silicon layer and gate structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables improved device performance and speed by effectively incorporating strain materials in the source/drain regions, enhancing carrier mobilities and facilitating the fabrication of high-speed, low-power semiconductor devices.
Implementation Method 1
in-situ doped strained material growth to form a plug of strained material that fills the opening and extends above the upper surface of the semiconductor material
Implementation Method 2
subsequent annealing, allowing for enhanced strain introduction
Data Source
AI summary
A transistor structure with improved device performance, and a method for forming the same is provided. The transistor structure is an SOI (silicon-on-insulator) transistor. In one embodiment, a silicon layer over the oxide layer is a relatively uniform film and in another embodiment, the silicon layer over the oxide layer is a silicon fin. The transistor devices include source/drain structures formed of a strain material that extends through the silicon layer, through the oxide layer and into the underlying substrate which may be silicon. The source/drain structures also include portions that extend above the upper surface of the silicon layer thereby providing an increased volume of the strain layer to provide added carrier mobility and higher performance.