SOI Transistor Stress Layer for Short Channel Effect Control
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Solution Overview
Problem
The miniaturization of semiconductor devices is hindered by Short Channel Effects (SCEs), which can lower device performance and cause failures, and existing methods struggle to apply sufficient stress to ultra-thin SOI MOS transistors to improve performance.
Innovation Solution
A semiconductor structure and manufacturing method involving a stress layer, buried oxide layer, and SOI layer are formed on a substrate, with a doped region and polycrystalline silicon region to create trenches and cavities, allowing for the introduction of stress to the channel, enhancing device performance by reducing SCEs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the channel length of MOS transistor is shortened to achieve higher integration density, then element density and integration degree are improved, but Short Channel Effects (SCEs) and Drain-Induced Barrier Lowering (DIBL) worsen, causing device performance degradation
Solution Approach 1:
The patent applies stress to the channel region by forming a stress layer with different lattice constant than the semiconductor layer, changing the physical state of the channel to improve carrier mobility and counteract Short Channel Effects, thereby maintaining device performance despite channel length reduction
Solution Approach 2:
The patent uses a composite structure consisting of a semiconductor layer on a substrate with a stress layer formed thereon. The stress layer is made of a material with different lattice constant (e.g., SiGe for NMOS, SiC for PMOS) to generate beneficial stress in the channel, creating a composite material system that addresses SCEs
2Reliability
If Silicon On Insulator (SOI) substrate is used to reduce Short Channel Effects and enhance device performance, then reliability and speed are improved, but the ability to apply sufficient stress to ultra-thin SOI MOS transistors deteriorates, limiting further performance improvement
Solution Approach 1:
The patent segments the stress application mechanism by separating the stress layer from the channel region, allowing independent optimization of stress magnitude and channel characteristics. The stress layer is formed as a distinct layer with thickness and composition controlled separately from the ultra-thin SOI channel
Solution Approach 2:
The patent applies stress locally to the channel region through a stress layer that is positioned adjacent to the channel. The stress layer has specific local properties (lattice constant, thickness, composition) tailored to generate the desired stress state in the channel region without affecting other parts of the device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively controls Short Channel Effects and improves device performance by introducing favorable stress to the semiconductor channel, enhancing electron and hole mobility depending on the device type.
Implementation Method 1
Internal mechanical stress of semiconductor devices is widely used to adjust performance of devices. SCEs can be improved by applying a stress to the channel.
Implementation Method 2
The stress layer is a silicon germanium layer, and the semiconductor layer is a silicon layer. The lattice constant of the silicon germanium layer is different from that of the silicon layer.
Data Source
AI summary
The present invention discloses a semiconductor structure and a method for manufacturing the same, which comprises providing a substrate, and forming a stress layer, a buried oxide layer, and an SOI layer on the substrate; forming a doped region of the stress layer arranged in a specific position in the stress layer; forming an oxide layer and a nitride layer on the SOI layer, and forming a first trench that etches the nitride layer, the oxide layer, the SOI layer, and the buried oxide layer, and stops on the upper surface of the stress layer, and exposes at least part of the doped region of the stress layer; forming a cavity by wet etching through the first trench to remove the doped region of the stress layer; forming a polycrystalline silicon region of the stress layer and a second trench by filling the cavity with polycrystalline silicon and etching back; forming an isolation region by filling the second trench. The semiconductor structure and the method for manufacturing the same disclosed in the present invention provide a favorable stress for the channel of the semiconductor device by introducing a stress layer and a stress induced zone set at specific positions depending on device type to help improving the performance of the semiconductor device.