SOI Semiconductor Device With Trench Oxide Thickness Control
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Solution Overview
Problem
Conventional semiconductor devices on SOI substrates face issues with non-uniform voltage application to side oxide films in trenches, leading to dielectric breakdown and capacitive coupling, which causes malfunction due to oxidation-induced stress and dislocation, making it difficult to achieve high breakdown voltage and reliability.
Innovation Solution
The semiconductor device features a specific thickness ratio of oxide films formed by thermal oxidation to ensure uniform voltage application across side oxide films, with a deep trench filled with n heavily doped layers and polycrystalline silicon, forming a closed loop structure that prevents dislocation and capacitive coupling, and includes multiple layers for enhanced isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If side oxide films are formed in the trench without controlling thickness ratio, then dielectric isolation is achieved, but non-uniform voltage application causes dielectric breakdown
Solution Approach 1:
The patent applies parameter changes by precisely controlling the thickness ratio of the third oxide film (formed on polycrystalline silicon in the trench) relative to the first oxide film (buried oxide). By setting this thickness ratio within a specific range of 0.05 to 0.50, the patent ensures uniform voltage distribution across all side oxide films during breakdown voltage application, preventing dielectric breakdown and achieving high reliability.
2Reliability
If oxidation is performed to form oxide films, then dielectric isolation is achieved, but oxidation-induced stress causes dislocation
Solution Approach 1:
The patent applies beforehand cushioning by forming the third oxide film on the polycrystalline silicon surface before final breakdown voltage application. This pre-formed oxide layer acts as a stress buffer that prevents oxidation-induced dislocation from propagating into the side oxide films during subsequent thermal processing, thereby maintaining isolation quality without dislocation.
3Reliability
If trench depth is increased to improve isolation, then element isolation is enhanced, but voltage non-uniformity increases
Solution Approach 1:
The patent applies local quality by forming the third oxide film specifically on the polycrystalline silicon surface within the trench, creating a localized oxide layer with controlled thickness. This local oxide formation compensates for the increased trench depth by ensuring that the voltage is uniformly distributed across all side oxide films, including those in deeper regions of the trench.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures high breakdown voltage, reduces dislocation, and enhances reliability by uniformly applying voltage and preventing capacitive coupling, resulting in a semiconductor device with improved dielectric strength and reduced defects.
Implementation Method 1
a specific thickness ratio of oxide films formed by thermal oxidation to ensure uniform voltage application across side oxide films
Data Source
AI summary
A dielectrically isolated semiconductor device of high reliability is provided by realizing a fine and deep element isolating region which can prevent dislocation of an oxide film as an insulation layer by oxidation-induced stress. The dielectrically isolated semiconductor device includes an SOI substrate supporting an active element layer deeper than an expanded distance of a depletion layer subjected to the highest voltage applied to the device, and an element isolating region which encloses the active element layer. The element isolating region contains a deep trench which comes into contact with the insulation layer, and which is filled with n heavily doped layers on both side walls, second insulation films each adjacent to the n heavily doped layer and a polycrystalline semiconductor layer formed between the second insulation films.