SOI Wafer Etching for Thin Semiconductor Substrates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for manufacturing ultra-thin semiconductor chips involve mechanical grinding, which introduces stress and damage to the functional layers, and require lamination and delamination processes that can leave residue on the front side.
Innovation Solution
A method using SOI wafers with masking and etching steps to reduce substrate thickness, avoiding mechanical stresses by removing layers through mask openings on both the front and rear sides, thereby preventing damage and residue formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If mechanical grinding is used to reduce substrate thickness, then the desired thinness is achieved, but mechanical stresses and damage to the functional layer are introduced
Solution Approach 1:
The patent replaces mechanical grinding with a chemical etching process. The etching solution chemically removes material from the carrier layer and insulation layer without mechanical contact, thereby achieving thickness reduction while avoiding mechanical stresses and damage to the functional layer.
Solution Approach 2:
The patent introduces an etching solution as an intermediary medium to remove material. The etching solution selectively etches the carrier layer and insulation layer through mask openings, enabling precise thickness control without direct mechanical action on the functional layer.
2Ease of manufacture
If lamination and delamination processes are used, then functional elements can be applied to the substrate, but foil remnants are left on the front side
Solution Approach 1:
The patent extracts the problematic lamination and delamination steps from the manufacturing process. By applying functional elements directly to the front side before etching and then removing the carrier layer, the process eliminates the need for lamination films and their associated residue problems.
Solution Approach 2:
The patent inverts the conventional sequence by first applying functional elements to the front side, then removing the carrier layer from the rear side. This reversal allows the front side to maintain its functional elements without requiring lamination and delamination, thus avoiding foil remnants.
3Length of moving object
If mask openings are configured to remove carrier layer and insulation layer, then the functional area is exposed and thinness is achieved, but the process complexity increases
Solution Approach 1:
The patent segments the etching process into distinct stages using different mask openings. The first mask opening protects the functional area while allowing etching of surrounding areas, and the second mask opening enables selective removal of the carrier layer. This segmentation allows complex thickness control to be achieved through systematic, manageable steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality of semiconductor devices by reducing mechanical stress and eliminating the need for grinding, allowing for precise control over thickness and shape, resulting in thinner, more reliable semiconductor devices.
Implementation Method 1
the functional area and, if necessary, the optional passivation layer are removed by etching the front side of the semiconductor substrate
Data Source
AI summary
A method for manufacturing a semiconductor device in which a semiconductor substrate is provided, including a SOI-wafer having a carrier layer defining a rear side, a functional layer defining a front side. An insulation layer is situated between the carrier layer and functional layer. The functional layer includes a functional area having functional structures. The front side is masked, a first mask opening defines an interior area containing the functional area. The functional layer is removed by etching the front side. The rear side is masked, a second mask opening being configured, and a circumferential edge of the second mask opening is spaced outwardly relative to an outer circumferential edge of the interior area. The carrier layer and the insulation layer are removed at least in the area of the second-mask opening by etching to expose the interior area.