SOI Wafer Buried Insulator Thickness Design for Lithography
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In photolithography operations, the variation in SOI layer thickness on SOI wafers leads to uneven exposure light reflection rates, causing pattern blurring and shifts, which affect device electric characteristics.
Innovation Solution
Designing the thickness of the buried insulator layer in the SOI wafer based on the exposure light wavelength using the expression d = (1/2) × (λ/n) × A, where d is the thickness, n is the refractive index, and A is an arbitrary positive integer, to maintain a constant reflection rate and ensure precise pattern formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the SOI layer thickness is reduced to improve device performance, then device characteristics are improved, but the reflection rate of exposure light varies widely causing pattern blurring and shifts
Solution Approach 1:
The patent introduces a buried insulator layer as an intermediary between the SOI layer and the substrate. This layer mediates the optical interaction by providing a controlled refractive index environment that stabilizes the reflection rate of exposure light, thereby preventing pattern blurring and shifts while allowing thin SOI layers to be used for improved device performance.
Solution Approach 2:
The patent changes the optical parameters of the system by controlling the thickness and refractive index of the buried insulator layer. By adjusting these parameters, the reflection rate of exposure light is stabilized, which resolves the issue of exposure uniformity while maintaining the benefits of thin SOI layers for device performance.
2Manufacturing precision
If the buried insulator layer thickness is not controlled, then manufacturing is simpler, but the reflection rate of exposure light varies causing pattern defects
Solution Approach 1:
The patent applies preliminary action by pre-controlling the thickness of the buried insulator layer during wafer fabrication, before the photolithography process. This advance control of the insulator layer thickness ensures that the reflection rate of exposure light remains stable during subsequent lithography operations, preventing pattern defects without adding complexity to the lithography process itself.
3Adaptability or versatility
If various wavelengths of exposure light are used for different device types, then device versatility is improved, but the exposure state of resist varies due to SOI layer thickness variation
Solution Approach 1:
The patent achieves universality by designing the buried insulator layer with specific thickness and refractive index characteristics that make the system effective across multiple wavelengths of exposure light. This allows the same wafer structure to be used for various device types (MEMS, RF devices, CPUs, logics, memories) with different lithography wavelength requirements, while maintaining exposure uniformity through the stabilized reflection rate provided by the insulator layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes the reflection rate of exposure light, preventing variations in the exposure state of the resist and enabling high-precision pattern formation, equivalent to bulk silicon conditions, thereby reducing device pattern variations and simplifying photolithography processes.
Implementation Method 1
the reflection rate of the exposure light is stabilized, thereby preventing variation in an exposure state of a resist
Implementation Method 2
The ion-implanted surface is then brought into close contact with a main surface of the other silicon wafer through the oxide film and the resultant wafer is then delaminated at the ion-implanted layer by performing a heat treatment at a temperature in the range of 300°C to 600°C
Implementation Method 3
high concentration oxygen ions are implanted into the interior of a silicon wafer to form an oxygen ion-implanted layer
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
The present invention is a method for manufacturing an SOI wafer that has an SOI layer formed on a buried insulator layer and is suitable for photolithography with an exposure light having a wavelength λ. The method comprises the steps of: designing a thickness of the buried insulator layer of the SOI wafer on the basis of the wavelength λ of the exposure light utilized for the photolithography that is to be performed on the SOI wafer after manufacturing; and fabricating the SOI wafer that has the SOI layer formed on the buried insulator layer having the designed thickness. As a result, there is provided a method for designing an SOI wafer and a method for manufacturing an SOI wafer that enable the variation in the reflection rate of the exposure light due to the variation in the SOI layer thickness and hence variation in the exposure state of a resist to be inhibited in a photolithography operation.