SoIS Fan-Out Interconnect Structure for Fine-Pitch Package Routing
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Solution Overview
Problem
The challenge in the semiconductor industry is to integrate high-functional electronic components into small packages while maintaining high performance and reducing costs, particularly in applications requiring miniaturization, where existing integrated fan-out package technologies face limitations in pitch and connectivity.
Innovation Solution
A method involving the formation of redistribution layers (RDLs) and through-molding vias (TMVs) on a carrier substrate, followed by the attachment of interconnect devices with conductive connectors, and the use of fine-pitch electrical routing to enhance connectivity and reduce package size, combined with a process for de-bonding and re-bonding to facilitate further processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If integrated fan out package technology is used to increase functional density, then the number of input/output pads and connectivity are improved, but the package size increases
Solution Approach 1:
The patent implements fine-pitch electrical routing with pitch of 0.2mm or less, transitioning from conventional larger pitch routing to ultra-fine pitch routing. This dimensional change in routing pitch enables higher functional density while maintaining compact package size, as the finer routing allows more connections within the same area.
Solution Approach 2:
The patent changes critical parameters including routing pitch (reduced to 0.2mm or less), via hole diameter (reduced to 0.05mm or less), and conductor trace width (reduced to 0.03mm or less). These parameter changes enable increased functional density without proportionally increasing package size, resolving the contradiction between connectivity and package dimensions.
2Productivity
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision requirements increase
Solution Approach 1:
The patent employs preliminary carrier substrate preparation with pre-formed contact pads and routing patterns before mounting semiconductor devices. This preliminary action establishes a precise framework that guides subsequent device placement and interconnection, enabling high integration density while maintaining manufacturing precision through pre-planned feature locations and dimensions.
Solution Approach 2:
The patent uses a carrier substrate as an intermediary structure that provides a stable platform for forming fine-pitch routing and contact pads. This intermediary carrier enables precise feature formation (0.05mm via holes, 0.03mm traces) that would be difficult to achieve directly on the final package, thereby enabling high integration density while managing manufacturing precision requirements.
3Area of stationary object
If fine-pitch routing is implemented to reduce package size, then package dimensions are reduced, but signal loss and manufacturing difficulty increase
Solution Approach 1:
The patent employs composite interconnect structures combining copper conductors with low-k dielectric materials for insulation. This composite material approach reduces signal loss in fine-pitch routing by using materials with optimized electrical properties, thereby enabling reduced package dimensions while maintaining signal integrity despite the increased routing density.
Data Source
AI summary
Semiconductor devices and methods of forming the semiconductor devices are described herein that are directed towards the formation of a system on integrated substrate (SoIS) package. The SoIS package includes an integrated fan out structure and a device redistribution structure for external connection to a plurality of semiconductor devices. The integrated fan out structure includes a plurality of local interconnect devices that electrically couple two of the semiconductor devices together. In some cases, the local interconnect device may be a silicon bus, a local silicon interconnect, an integrated passive device, an integrated voltage regulator, or the like. The integrated fan out structure may be fabricated in wafer or panel form and then singulated into multiple integrated fan out structures. The SoIS package may also include an interposer connected to the integrated fan out structure for external connection to the SoIS package.