Solder Paste Layout for Low-Void SMT Solder Joints
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Solution Overview
Problem
The formation of voids or blowholes in soldering points during the Surface Mount Technology (SMT) process leads to reduced service life and increased reject rates of printed circuit boards, as excess flux cannot completely escape, causing bubbles to accumulate and negatively impact thermal conductivity and electrical connections.
Innovation Solution
A method that involves applying solder paste with minimal overlap onto the solder resist layer, utilizing the capillary effect to prevent premature outgassing and minimize void formation by ensuring excess flux can escape through strategically designed outgassing channels, reducing the amount of solder paste required by approximately 40%.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If solder paste is applied directly onto the contact surfaces, then good electrical connection is achieved, but void formation increases due to flux entrapment
Solution Approach 1:
The solder paste application area is segmented into two distinct zones: a first area directly on the contact surface for electrical connection, and a second area on the solder mask layer forming an outgassing channel. This segmentation allows flux to escape through the second area while solder bonds at the first area, resolving the contradiction between connection quality and void prevention.
Solution Approach 2:
The solder mask layer serves as an intermediary medium between the contact surface and the external environment. By applying solder paste to the solder mask layer in the second area, it creates a controlled outgassing pathway that mediates flux escape without compromising the solder joint's electrical connection function.
2Productivity
If larger areas of solder surface are covered by components, then more connections are made, but void formation increases due to longer flux escape paths
Solution Approach 1:
The outgassing channel is extended into the vertical dimension by applying solder paste to the solder mask layer above the contact surface. This creates a three-dimensional flux escape pathway that bypasses the horizontal distance constraint, allowing flux to escape vertically even when components cover large areas of the contact surface.
3Manufacturing precision
If conventional solder paste application is used, then complete coverage is achieved, but reject rate increases due to void formation
Solution Approach 1:
Different functional qualities are assigned to different locations: the first area on the contact surface ensures electrical connection quality, while the second area on the solder mask layer provides outgassing functionality. This local differentiation allows complete coverage without uniform application, reducing voids while maintaining connection integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Significantly reduces void formation in solder joints, minimizing rejects and increasing the service life of electronic components, while allowing for more efficient solder paste usage and improved thermal conductivity.
Implementation Method 1
utilizing the capillary effect to prevent premature outgassing and minimize void formation by ensuring excess flux can escape through strategically designed outgassing channels
Data Source
Figure 1
Figure 2(a)~2(c)
Figure 3(a)~3(b)
AI summary
The invention relates to a method for the soldering connection at least of one electronic component (104, 204, 304, 404, 504) to a carrier plate (100, 200, 300, 400, 500), wherein the carrier plate has at least one carrier plate contact surface (102, 202, 302, 402, 502) and the at least one electronic component has at least one corresponding component contact surface (105), wherein the at least one carrier plate contact surface is surrounded by a solder resist layer (101, 201, 301, 401, 401) that abuts the at least one carrier plate contact surface, wherein the method comprises the following steps: a) applying, at least in sections, solder paste (106, 206, 306, 406, 506) to the solder resist layer (101, 201, 301, 401, 501) and with minimal overlapping with the carrier plate contact surface (102, 202, 302, 402, 502) abutting the solder resist layer; b) providing the carrier plate with the at least one electronic component (104, 204, 304, 404, 504), wherein the at least one component contact surface (105) at least partially covers the corresponding at least one carrier plate contact surface (102, 202, 302, 402, 502); and c) heating the solder paste (106, 206, 306, 406, 506) to produce a soldered connection between the carrier plate and the at least one component.