Solder Resist Underlayer Structure for Wafer Package Warpage Control
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Solution Overview
Problem
Current wafer level packaging technologies face challenges in achieving efficient warpage control and reducing manufacturing costs, particularly in the formation of package structures with conductive pillars and semiconductor dies, where the existing methods are complex and costly.
Innovation Solution
The use of a solder resist layer with a specific thickness range and filler composition, combined with a debond layer, allows for the formation of openings that enable the placement and encapsulation of conductive pillars and semiconductor dies, reducing warpage and manufacturing complexity through photolithography and electroplating processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional wafer level packaging methods are used, then manufacturing process is established, but warpage control is insufficient and manufacturing cost is high
Solution Approach 1:
The packaging structure is divided into distinct functional layers: a substrate layer, a solder resist layer with openings, and a encapsulant layer. This segmentation allows each layer to be optimized independently for its specific function, improving warpage control while simplifying the overall manufacturing process through modular construction
Solution Approach 2:
The solder resist layer is designed with specific parameter ranges: thickness of 5-20 micrometers and filler content of 20-40 weight percent. These parameter optimizations enable the layer to provide adequate mechanical support for warpage control while maintaining processability and cost-effectiveness
2Manufacturing precision
If solder resist layer with filler is used, then warpage control is improved, but manufacturing cost may increase
Solution Approach 1:
The filler content is optimized to 20-40 weight percent, which provides sufficient mechanical reinforcement for warpage control without excessive material consumption. This parameter optimization balances performance requirements with cost considerations by avoiding both under-reinforcement and over-reinforcement
Solution Approach 2:
The solder resist layer with filler is applied specifically where needed - in the regions requiring warpage control - rather than uniformly throughout the entire package structure. This localized application reduces overall filler material consumption while maintaining effectiveness in critical areas
3Ease of manufacture
If openings are formed in solder resist layer, then conductive pillars and dies can be placed, but manufacturing process becomes more complex
Solution Approach 1:
The openings in the solder resist layer are formed in advance using photolithography before component placement. This preliminary action prepares the structure for subsequent assembly steps, allowing conductive pillars and dies to be placed directly into the pre-formed openings without requiring complex in-situ fabrication processes
Solution Approach 2:
The solder resist layer with openings serves as an intermediary structure that facilitates the placement of conductive pillars and dies. It provides a controlled interface between the substrate and the components, enabling precise positioning while simplifying the overall manufacturing flow through its mediating function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved warpage control and reduced manufacturing costs by enabling the efficient formation of package structures with dual-side terminals, enhancing the reliability and yield of semiconductor packages.
Implementation Method 1
a solder resist layer with a specific thickness range and filler composition
Implementation Method 2
reducing warpage and manufacturing complexity through photolithography and electroplating processes
Implementation Method 3
reducing warpage and manufacturing complexity through photolithography and electroplating processes
Data Source
AI summary
A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.