Solderless Interposer Fixture for Bare Chip Dynamic Testing
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Solution Overview
Problem
Testing bare wide bandgap (WBG) power devices, such as SiC MOSFETs, is challenging due to time-consuming packaging, physical damage during soldering, and high parasitic inductance issues that compromise accuracy and reliability of dynamic parameter characterization.
Innovation Solution
A device using flexible solderless interposers and pressing plates to establish electrical connections without soldering, minimizing parasitic inductance and enabling quick, accurate testing of bare chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If soldering is used to connect bare chips to test circuits, then reliable electrical connections are achieved, but the bare chips suffer physical damage and cannot be sold
Solution Approach 1:
The patent introduces an intermediary structure (test substrate with contact pads and conductive patterns) that mediates between the bare chip and the testing system. This intermediary allows electrical connections to be established through controlled contact mechanisms (such as spring-loaded contacts or probe cards) rather than direct soldering, thereby maintaining connection reliability while preventing physical damage to the fragile bare chips.
Solution Approach 2:
The patent replaces the thermal-mechanical soldering process with a mechanical contact-based connection system. Instead of using heat and molten solder to create permanent bonds, the system uses mechanically actuated contacts (such as spring fingers or flexible probes) that apply controlled pressure to establish electrical connections, eliminating the thermal damage and mechanical stress associated with soldering.
2Measurement precision
If complete packages are created for testing bare chips, then accurate dynamic parameter characterization is achieved, but the packaging process takes a month or more
Solution Approach 1:
The patent implements preliminary action by pre-configuring test substrates with complete circuitry, contact pads, and mounting structures before the actual testing begins. These substrates are prepared in advance with all necessary electrical connections and mechanical support structures, allowing bare chips to be directly mounted and tested without requiring time-consuming packaging processes. The preliminary preparation of test fixtures enables rapid chip-to-test transitions.
Solution Approach 2:
The patent creates universal test substrates that can accommodate multiple different bare chip types and configurations. These multi-functional substrates integrate various test circuits, contact patterns, and mounting structures that can be reused across different testing scenarios, eliminating the need to create custom packages for each chip type and significantly reducing preparation time while maintaining measurement accuracy.
3Reliability
If wire-bonding is used to create temporary packages, then electrical connections are established, but the process takes a week or more and requires intricate work
Solution Approach 1:
The patent extracts and eliminates the wire-bonding step from the testing process entirely. Instead of creating temporary packages with wire bonds, the system uses direct contact methods where electrical connections are established through contact pads and pressure-based interfaces. This extraction of the wire-bonding process removes the time-consuming and intricate manual or automated wire bonding operations while maintaining reliable electrical connectivity through simpler contact mechanisms.
4Ease of operation
If probes or pins are used to establish electrical contact, then no soldering is required, but scratches or dents are created on bare chips
Solution Approach 1:
The patent applies parameter changes by carefully controlling the physical parameters of the contact process, including contact pressure, contact area distribution, and material hardness. By optimizing these parameters, the system achieves reliable electrical contact through distributed pressure on contact pads rather than concentrated point contacts, preventing scratches and dents while maintaining ease of operation and reversibility.
Data Source
AI summary
A device for testing characteristics of a first bare chip includes a main PCB including a main circuit; a first interposer arranged on the main PCB; a second interposer arranged over the first interposer and the main PCB, where the first and second bare chips are arranged between the first and second interposers for testing the first bare chip; and at least one pressing plate configured to apply a pressing force against the second interposer for pressing the second interposer toward the first interposer and the main PCB. The first interposer provides first electrical connections with the first and second bare chips and the main circuit by contact without soldering, and the second interposer is configured to provide second electrical connections with the first and second bare chips and the main circuit by contact without soldering. The pressing force enhances the first and second electrical connections during the testing.


