SONOS FinFET Memory Cell With Integrated Logic Gate Formation
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Solution Overview
Problem
Current technologies face challenges in integrating memory processes with logic processes in silicon-oxide-nitride-oxide-silicon (SONOS) memory cells for FinFET, as they require separate fabrication steps for memory and logic regions, leading to increased complexity and cost.
Innovation Solution
A method is developed to form a silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for FinFET, where a control gate with a charge trapping layer and a selective metal gate are formed simultaneously with a gate in the logic region, allowing for the integration of memory and logic processes by depositing and patterning charge trapping and control gate materials, followed by the deposition and patterning of dielectric and gate electrode layers, and replacing selective gates with metal gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate fabrication steps are used for memory and logic regions, then manufacturing precision can be maintained for each region, but device complexity and manufacturing time increase
Solution Approach 1:
The patent combines memory region fabrication and logic region fabrication into a single integrated process flow. Both regions are formed simultaneously using shared deposition and patterning steps, eliminating the need for separate fabrication sequences while maintaining the distinct structural requirements of each region through selective material deposition and patterning
2Reliability
If separate fabrication steps are used for memory and logic regions, then each region can be optimized independently, but manufacturing time and cost increase
Solution Approach 1:
The patent employs universal deposition and patterning processes that serve both memory and logic region fabrication simultaneously. The same equipment and process parameters are used for both regions, allowing independent optimization of each region's structure while executing both fabrications in parallel within a single manufacturing cycle
3Manufacturing precision
If control gate and selective gate are formed in separate steps, then gate structure precision is improved, but process complexity increases
Solution Approach 1:
The patent segments the gate formation into distinct functional components (control gate with charge trapping layer and selective metal gate) that are deposited and patterned in an integrated sequence. Each gate structure maintains its precise structural requirements through selective material deposition, while the overall process is streamlined by executing both gate formations within a unified manufacturing flow
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the concurrent formation of memory and logic components on a fin, simplifying the fabrication process, reducing complexity, and integrating memory processes into logic processes, thereby improving manufacturing efficiency and reducing costs.
Implementation Method 1
the control gate includes a charge trapping layer and a control electrode, wherein the charge trapping layer is sandwiched by the fin and the control electrode
Implementation Method 2
A charge trapping material and a control gate material are sequentially deposited to cover the fin and the substrate blanketly
Implementation Method 3
The selective gate and the gate are replaced by a selective metal gate and a metal gate respectively
Data Source
AI summary
A silicon-oxide-nitride-oxide-silicon (SONOS) memory cell for FinFET includes a fin, a control gate and a selective metal gate. The fin is on a top surface of a substrate, wherein the fin has two sidewalls and a top surface, and the fin includes a memory region and a logic region. The control gate is disposed over the fin of the memory region and covers the two sidewalls and the top surface of the fin, wherein the control gate includes a charge trapping layer and a control electrode, wherein the charge trapping layer is sandwiched by the fin and the control electrode. The selective metal gate is disposed over the fin adjacent to the control gate and covers the two sidewalls and the top surface of the fin. The present invention also provides a method of forming said silicon-oxide-nitride-oxide-silicon (SONOS) memory cell.