SONOS NVM Integration in Sub-90 nm CMOS via High-k Dielectrics

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Solution Overview

Problem

Current methods for integrating silicon oxide nitride oxide silicon (SONOS) non-volatile memory (NVM) into a standard CMOS foundry process flow face challenges in minimizing process overhead, managing programming voltages, and maintaining charge retention while reducing leakage currents as CMOS geometries shrink, leading to complex circuit designs and increased power consumption.

Innovation Solution

A method is introduced that adds only two extra masking steps and utilizes new material sets, such as high permittivity gate oxides and atomic layer deposition, to integrate SONOS NVM into a standard CMOS foundry process flow, enhancing charge tunneling behavior and reducing leakage currents, while maintaining reasonable programming voltages and ease of integration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If SONOS NVM is integrated into standard CMOS foundry process flow, then process overhead is reduced and integration is simplified, but additional process steps and material sets are still required

Engineering Contradiction:

Improveintegration simplicityVSAvoidprocess steps

Core Design Contradiction:

Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent combines SONOS NVM fabrication with standard CMOS process steps by integrating the formation of the tunnel oxide, charge storage layer, and blocking oxide into existing CMOS process sequences. The SONOS stack is formed using the same deposition and oxidation equipment already present in the CMOS foundry, merging two separate process flows into one unified sequence that produces both CMOS devices and SONOS NVM devices simultaneously.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent employs universal process modules that serve dual purposes: standard CMOS transistors and embedded SONOS NVM cells share common process steps including gate oxide formation, channel doping, and interconnect fabrication. The same deposition chambers and oxidation furnaces used for CMOS devices are also used to create the SONOS memory stack, making the manufacturing equipment multi-functional and eliminating the need for dedicated NVM fabrication lines.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Use of energy by moving object

If memory stack is made thinner to reduce programming voltage, then programming voltage is reduced, but charge retention deteriorates and leakage increases

Engineering Contradiction:

Improveprogramming voltageVSAvoidcharge retention

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent optimizes the thickness parameters of the SONOS stack layers to achieve a balance between programming voltage and charge retention. The tunnel oxide is formed at precisely controlled thicknesses (e.g., 8-15 nm) that allow efficient charge injection at reduced voltages while the blocking oxide is made sufficiently thick (e.g., 5-10 nm) to prevent charge leakage and maintain retention. The charge storage layer thickness is also optimized to provide adequate charge capacity while maintaining the overall stack thickness within limits that enable low-voltage operation.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent uses a composite SONOS stack structure consisting of multiple functional layers: a thin high-quality tunnel oxide for efficient charge injection, a nitride-based charge storage layer for charge trapping, and a thicker blocking oxide to prevent charge loss. This composite structure allows the system to achieve low programming voltages through the thin tunnel oxide while maintaining excellent charge retention through the combined barrier properties of the multi-layer stack, resolving the contradiction between voltage reduction and retention maintenance.

Inventive Principle:

Principle #40Composite materials

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for efficient integration of SONOS NVM into sub-90 nm CMOS devices with reduced processing burden, improved charge retention, and lower operating voltages, addressing the complexity and power consumption issues associated with shrinking CMOS geometries.

Implementation Method 1

enhancing charge tunneling behavior

Methodology Applied

Scientific EffectQuantum mechanical tunneling:

Implementation Method 2

high permittivity gate oxides... reducing leakage currents

Methodology Applied

Scientific EffectDielectric insulation: Dielectric

Implementation Method 3

utilizes new material sets, such as high permittivity gate oxides and atomic layer deposition

Methodology Applied

Scientific EffectAtomic layer deposition:

Data Source

PatentUS8409950B1Method for integrating SONOS non-volatile memory into a sub-90 nm standard CMOS foundry process flow

Publication Date: 2013.04.02 NORTHROP GRUMMAN SYSTEMS CORP

AI summary

An embodiment of a method is disclosed to integrate silicon oxide nitride oxide silicon (SONOS) non-volatile memory (NVM) into a standard sub-90 nm complementary metal oxide semiconductor (CMOS) semiconductor foundry process flow. An embodiment of the method adds a few additional steps to a standard CMOS foundry process flow and makes minor changes to the rest of the baseline CMOS foundry process flow to form a new process module that includes both CMOS devices and an embedded SONOS NVM. An embodiment of the method utilizes new material sets (which are not utilized at larger nodes) that enhance NVM performance by improving charge tunneling behavior and reducing leakage currents. Furthermore, an embodiment of the method integrates CMOS with SONOS NVM at ever-shrinking dimensions while enhancing the NVM performance, without performing extra, costly processing steps.