SONOS Memory Gate Structure with Localized Pad Layer
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Solution Overview
Problem
SONOS memory devices face challenges in simultaneously improving programming/erasing characteristics and retention characteristics due to the trade-off between these properties in the oxide-nitride-oxide layer, leading to suboptimal performance.
Innovation Solution
The method involves forming a substrate with a cell region and a non-cell region, depositing a charge storing film, a tunneling dielectric layer, and a top insulating layer, followed by the formation of isolation trenches and gate layers, which includes a conductive pad layer that can be incorporated into the gate electrode, to create optimized memory gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the oxide-nitride-oxide layer is optimized for programming/erasing characteristics, then programming and erasing speeds improve, but retention characteristics deteriorate
Solution Approach 1:
The patent applies local quality by forming a pad layer specifically in the cell region with a different composition (silicon nitride or silicon oxynitride) than the surrounding non-cell region. This localized modification allows the charge storing film in the cell region to achieve optimal programming/erasing characteristics through hot electron injection, while the overall device structure maintains good retention characteristics. The pad layer's specific location and material properties create locally optimized conditions without compromising global device performance.
2Reliability
If the oxide-nitride-oxide layer is optimized for retention characteristics, then data retention improves, but programming/erasing characteristics deteriorate
Solution Approach 1:
The invention resolves this contradiction by implementing local quality through a strategically positioned pad layer in the cell region. The pad layer made of silicon nitride or silicon oxynitride creates locally enhanced electric field conditions that facilitate efficient hot electron injection for programming and erasing operations. Meanwhile, the bulk oxide-nitride-oxide structure in the non-cell region maintains its integrity for reliable data retention, achieving both fast programming/erasing and good retention performance through spatially differentiated optimization.
3Ease of manufacture
If a conventional STI process is used with pad oxide and pad nitride deposited before charge storing film, then manufacturing simplicity is maintained, but charge storing film quality deteriorates
Solution Approach 1:
The patent applies preliminary action by depositing the charge storing film (tunnel oxide, nitride layer, and top oxide) before forming the shallow trench isolation structures. This sequence ensures that the charge storing film is formed on a clean substrate surface without exposure to etchants and processing conditions that would occur during conventional STI processes. The charge storing film is then protected by subsequent isolation formation steps, maintaining its high quality while still allowing for standard isolation techniques to be used later in the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the quality of the charge storing film and improves the trade-off between programming and retention characteristics, leading to better performance in SONOS memory devices by maintaining the integrity of the ONO layer during processing.
Implementation Method 1
when a program voltage is applied to the gate of the transistor and a drain of the cell, a hot electron is formed and then surrounded by a nitride film being at an area adjacent to the drain
Implementation Method 2
forming a tunneling dielectric layer
Data Source
AI summary
In an non-limiting example, we provide a substrate having a cell region, and non-cell regions. We form a tunneling dielectric layer, a charge storing layer, a top insulating layer (e.g., ONO), over the substrate. Then we form a conductive pad layer over the top insulating layer. We form isolation trenches in the pad layer, the charge storing layer and the tunneling dielectric layer and into the substrate. We form isolation regions in the isolation trenches. We remove the pad layer, charge storing layer and the tunneling dielectric layer in the non-cell regions. We form a gate layer over the pad layer and the substrate surface. We complete to form the memory (e.g., SONOS) device in the cell region and other devices in the non-cell regions of the substrate.