SONOS Transistor Dielectric Thinning for CMOS Integration
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Solution Overview
Problem
The integration of dissimilar transistors, such as non-volatile memory (NVM) and metal-oxide-semiconductor (MOS) transistors, in system-on-chip (SOC) architecture is challenging, especially as transistors are scaled to smaller geometries, due to differences in their fabrication processes.
Innovation Solution
A method for forming memory cells that involves depositing and patterning a gate layer over a dielectric stack on a substrate to form a gate for NVM transistors, thinning the dielectric stack in source and drain regions, and implanting dopants to create a lightly-doped drain adjacent to the gate, while integrating these processes within a CMOS fabrication flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If NVM and MOS transistors are integrated using standard CMOS process flows, then system-on-chip architecture is achieved, but fabrication process compatibility and manufacturing precision deteriorate due to dissimilar transistor structures
Solution Approach 1:
The patent applies local quality by making the dielectric stack thickness variable across different regions of the NVM transistor. The gate dielectric is thinner in channel regions and thicker in source/drain regions, allowing each region to have optimized properties for its specific function while using a single continuous fabrication process
Solution Approach 2:
The patent changes the physical parameter of dielectric thickness during fabrication by performing selective thinning operations. The dielectric stack thickness is modified from an initial uniform value to different final values in different regions through controlled etching processes, enabling region-specific optimization within a standard CMOS flow
2Area of moving object
If transistors are scaled to smaller geometries, then device density is improved, but fabrication difficulty and process complexity increase
Solution Approach 1:
The patent segments the fabrication process into distinct stages: forming a uniform dielectric stack, selective thinning in source/drain regions, and region-specific dopant implantation. This segmentation allows complex regional variations to be achieved through simple, repeatable process steps rather than requiring complex single-step operations
Solution Approach 2:
The patent performs preliminary action by forming the complete dielectric stack with uniform thickness before any selective thinning operations. This preliminary uniform structure serves as a foundation that simplifies subsequent processing, as the selective thinning can be achieved through standard etching techniques rather than requiring complex direct patterning
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables effective integration of NVM and MOS transistors by thinning the dielectric stack in source and drain regions, allowing for the formation of lightly-doped drains, which improves the fabrication process and enhances the integration of NVM transistors into CMOS processes, addressing the challenges of scaling to smaller geometries.
Implementation Method 1
a tunneling layer overlying a surface of the substrate
Implementation Method 2
implanting dopants into S/D regions of the NVM transistor through the thinned dielectric stack
Data Source
AI summary
A method of forming a transistor is described. In one embodiment the method includes: forming a channel of a transistor in a surface of a substrate; forming a dielectric stack including a first oxide layer overlying the surface of the substrate, a middle layer comprising nitride overlying the first oxide layer and a second oxide layer overlying the middle layer; forming over the dielectric stack a mask exposing source and drain (S/D) regions of the transistor; etching the dielectric stack through the mask to thin the dielectric stack by removing the second oxide layer and at least a first portion of the middle layer in S/D regions of the transistor; and implanting dopants into S/D regions of the transistor through the thinned dielectric stack to form a lightly-doped drain (LDD) adjacent to the channel of the transistor. Other embodiments are also described.