Tri-Layered Nitride Charge Trap for SONOS Memory Retention
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Solution Overview
Problem
Conventional SONOS memory structures face challenges in charge capture and data retention due to limitations in the nitride charge trap layer's ability to trap and retain electrons or holes effectively, particularly during erase operations and over the end of life (EoL) memory window.
Innovation Solution
A tri-layered charge-trapping layer is introduced, comprising a bottom nitride layer, a middle nitride layer with a higher concentration, and a top nitride layer, sandwiched between tunnel and blocking dielectric layers, creating a saddle-shaped energy band that enhances charge trapping and retention, improving data retention and EoL memory window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional single-layer nitride charge trap layer is used in SONOS memory structure, then the structure is simple and manufacturing is easier, but the charge capture and retention ability is insufficient
Solution Approach 1:
The charge trap layer is segmented into three distinct nitride layers (first nitride layer, second nitride layer, and third nitride layer) with different thicknesses and positions. This segmentation allows each layer to contribute differently to charge trapping, with the middle third nitride layer having higher concentration to enhance overall charge capture ability while maintaining structural organization
Solution Approach 2:
Different regions of the charge trap structure are given different properties: the first and second nitride layers have lower concentrations and serve as outer protective layers, while the third nitride layer in the middle has higher concentration to maximize charge trapping. This local differentiation optimizes both charge capture efficiency and structural function
2Reliability
If the nitride layer concentration is increased to improve charge trapping, then charge capture ability improves, but the energy band structure becomes less favorable for retention
Solution Approach 1:
The concentration parameter of nitride layers is varied across different layers. The third nitride layer has a higher nitride concentration than the first and second layers, creating a concentration gradient that forms a saddle-shaped energy band. This parameter variation optimizes both charge trapping efficiency and energy band structure for improved retention
Solution Approach 2:
The charge trap structure uses a composite of multiple nitride layers with different concentrations rather than a uniform single-layer structure. This composite approach allows the formation of a saddle-shaped energy band that simultaneously enhances charge capture and improves retention stability
3Reliability
If a tri-layered charge trap structure is implemented to improve charge retention, then data retention and EoL memory window improve, but the manufacturing process becomes more complex
Solution Approach 1:
The charge trap layer is divided into three segments (first, second, and third nitride layers) that can be formed using sequential deposition processes. Each layer is deposited with controlled thickness and concentration, allowing standard semiconductor manufacturing techniques to be applied while achieving the complex tri-layered structure
Solution Approach 2:
Manufacturing parameters such as deposition concentration and layer thickness are systematically varied to create the tri-layered structure. The third layer is deposited with higher nitride concentration, and the layers are formed with specific thickness ratios that collectively create the desired saddle-shaped energy band without requiring fundamentally new manufacturing capabilities
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The tri-layered charge-trapping structure significantly improves charge capture and retention capabilities, enhancing data retention and EoL memory window performance without altering the semiconductor memory cell structure dimensions, allowing for increased device density and compatibility with existing SONOS configurations.
Implementation Method 1
the tri-layered charge-trapping layer includes a bottom nitride layer formed on the substrate, a top nitride layer formed on the bottom nitride layer, and a middle nitride layer sandwiched between the bottom nitride layer and the top nitride layer
Implementation Method 2
the nitride charge trap layer traps the electrons or holes that penetrate through the charge tunnel layer
Implementation Method 3
the oxide charge block layer prevents the electrons or holes that escape the charge trap layer from reaching the silicon during program or erase operations
Implementation Method 4
a high electric field is induced thus electrons or holes are accelerated and injected into the oxide charge tunnel layer from the source
Data Source
AI summary
A semiconductor memory cell structure includes a substrate, a tunnel dielectric layer formed on the substrate, a blocking dielectric layer formed on the substrate, a control gate formed on the blocking dielectric layer, and a tri-layered charge-trapping layer sandwiched between the tunnel dielectric layer and the blocking dielectric layer. Furthermore, the tri-layered charge-trapping layer includes a bottom nitride layer formed on the substrate, a top nitride layer formed on the bottom nitride layer, and a middle nitride layer sandwiched between the bottom nitride layer and the top nitride layer. The bottom nitride layer includes a first nitride concentration, the top nitride layer includes a second nitride concentration, and the middle nitride layer includes a third nitride concentration. And the third nitride concentration is larger than the first nitride concentration and the second nitride concentration.