SOT-MRAM 4T1M Layout for Higher Write Current Density
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Solution Overview
Problem
Conventional spin-orbit torque magnetic random access memory (SOT-MRAM) designs face challenges in reducing layout area and improving current efficiency due to their three-terminal architecture, which requires additional components and higher operating currents, hindering miniaturization and current usage efficiency.
Innovation Solution
The proposed SOT-MRAM circuit employs a 4T1M architecture with two read transistors and two write transistors connected in parallel, eliminating the need for additional isolating word lines and allowing for different read/write active area widths, thereby reducing layout area and enhancing current efficiency by doubling the operating current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If three-terminal architecture is adopted for SOT-MRAM, then current efficiency is improved and write current doesn't pass through magnetic tunnel junction, but layout area increases due to more components required
Solution Approach 1:
The patent merges the read and write transistor structures by sharing common word lines and bit lines. Specifically, the first and second read transistors share common word lines WL1 and WL2, and the first and second write transistors share common word lines WL1 and WL2. This merging reduces the total number of unique components and interconnects, thereby reducing layout area while maintaining the three-terminal architecture's current efficiency benefits
Solution Approach 2:
The word lines WL1 and WL2 serve multiple functions: they act as gate electrodes for both read transistors and write transistors, and they serve as current paths for both reading and writing operations. This multi-functionality reduces the overall component count and simplifies the layout structure, addressing the area increase problem
2Area of stationary object
If common word line or common bit line approach is used, then layout area is reduced, but additional isolating word lines are required or gate widths must be identical
Solution Approach 1:
The patent segments the transistor structures into distinct first and second read transistors and first and second write transistors, each with dedicated active areas. This segmentation allows different gate widths for read and write transistors while sharing common word lines, eliminating the need for identical gate widths and additional isolating word lines
Solution Approach 2:
The patent applies local quality by allowing different gate widths for different transistor types (read vs. write) based on their specific operational requirements. The first read transistor and second read transistor can have different gate widths optimized for their respective functions, while still sharing common word lines, thus reducing structural constraints
3Reliability
If conventional SOT-MRAM design is used, then basic functionality is achieved, but current efficiency is low requiring higher operating currents
Solution Approach 1:
The patent implements dynamic current routing where the same physical current path can be configured for different operations. By controlling which transistors are active through the shared word lines, the system dynamically routes current efficiently during read and write operations, improving overall current efficiency compared to static conventional designs
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the required layout area and improves current efficiency by allowing double operating current to the memory unit, addressing the inefficiencies of conventional SOT-MRAM designs and enabling more compact device miniaturization.
Implementation Method 1
spin-orbit torque magnetic random access memory (SOT-MRAM)
Implementation Method 2
magnetic tunnel junction
Data Source
AI summary
The present invention provides a spin-orbit torque magnetic random access memory (SOT-MRAM) circuit, including a read transistor pair with two read transistors in parallel, a write transistor pair with two write transistors in parallel, a SOT memory cell with a magnetic tunnel junction (MTJ) and a SOT layer, wherein one end of the MTJ is connected to the source of the read transistor pair and the other end of the MTJ is connected to the SOT layer, and one end of the SOT layer is connected to a source line and the other of the SOT layer is connected to the source of the write transistor pair, a read bit line is connected to the drain of the read transistor pair and a write bit line is connected to the drain of the read transistor.