Spin-Orbit Torque TCAM Circuit Separates Read and Write Paths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Ternary content addressable memory (TCAM) implementations face challenges with high power consumption, large semiconductor footprints, and limited speed due to low tunnel magnetoresistance properties and high write currents in existing CMOS and spin-transfer torque (STT) magnetic random-access memory (MRAM) cells.
Innovation Solution
The use of spin-orbit torque (SOT) magnetic tunnel junction (MTJ) elements with separate read and write paths, employing higher tunnel magnetoresistance and reducing the need for high write currents, is introduced to enhance TCAM performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If spin-transfer torque (STT) magnetic random-access memory (MRAM) cells are used for TCAM implementation, then non-volatile storage is achieved, but search speed is limited due to low tunnel magnetoresistance properties
Solution Approach 1:
The patent changes the fundamental parameter of tunnel magnetoresistance by transitioning from STT-MRAM to SOT-MRAM technology. SOT-MRAM achieves higher tunnel magnetoresistance ratios (exceeding 200%) through spin-orbit coupling mechanisms, directly resolving the speed limitation while preserving non-volatile storage capabilities
Solution Approach 2:
The patent replaces the spin-transfer torque mechanism with a spin-orbit torque mechanism. This substitution uses spin Hall effect or Rashba effect to generate spin current that acts on the magnetization, eliminating the need for high current through the tunnel barrier and enabling faster switching speeds
2Ease of manufacture
If high write currents are used in STT MRAM-based TCAMs, then data writing is achieved, but power dissipation increases and feature sizes increase
Solution Approach 1:
The patent segments the current path into separate read and write current paths. Write current flows through the spin Hall effect layer to generate spin torque, while read current flows through the MTJ stack. This segmentation allows low-power read operations and reduces the power penalty of write operations, directly addressing the power dissipation issue
Solution Approach 2:
The patent introduces a spin Hall effect layer as an intermediary that converts charge current into spin current. This mediator generates the necessary spin torque for magnetization switching without requiring high current through the MTJ tunnel barrier, thereby reducing power dissipation and allowing smaller feature sizes
3Adaptability or versatility
If CMOS-based CAMs are used, then binary content addressing is achieved, but static power dissipation and area overhead increase as density increases
Solution Approach 1:
The patent employs magnetic tunnel junctions with spin-orbit torque as the core memory element, which provides non-volatile storage. This eliminates the need for continuous refresh operations required by volatile CMOS memory, thereby eliminating static power dissipation while maintaining content addressing functionality
Solution Approach 2:
The patent uses a composite structure combining spin Hall effect materials (such as topological insulators or heavy metals) with magnetic tunnel junctions. This composite material system enables efficient spin-orbit coupling for writing while maintaining high tunnel magnetoresistance for reading, achieving both low power and high density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption, increases search speed, and extends device lifetime by minimizing wear on tunnel barrier layers, while maintaining compact size and low static power dissipation.
Implementation Method 1
having a spin hall effect (SHE) layer coupled in a first configuration across complemented write inputs
Implementation Method 2
employing higher tunnel magnetoresistance
Data Source
AI summary
Ternary content addressable memory (TCAM) circuits are provided herein. In one example implementation, a TCAM circuit can include a first spin-orbit torque (SOT) magnetic tunnel junction (MTJ) element having a pinned layer coupled to a first read transistor controlled by a first search line, and having a spin hall effect (SHE) layer coupled in a first configuration across complemented write inputs. The TCAM circuit can include a second SOT MTJ element having a pinned layer coupled to a second read transistor controlled by a second search line, and having a SHE layer coupled in a second configuration across the complemented write inputs. The TCAM circuit can include a bias transistor configured to provide a bias voltage to drain terminals of the first read transistor and the second read transistor, and a voltage keeper element that couples the drain terminals to a match indicator line.


