Source Bus Bar FET Layout for Thermal Isolation in Transistor Arrays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Heat interference occurs between multiple unit FET groups in the extending direction of fingers in semiconductor devices, affecting their operational consistency.
Innovation Solution
A semiconductor device design featuring a source bus bar overlapping via holes that penetrate through the substrate, with transistors arranged to sandwich the bus bar, and incorporating thermal isolation via holes and metal layers to reduce heat interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If multiple unit FET groups are arranged in the extending direction of fingers to increase device capacity, then the device can handle higher current and power, but heat interference occurs between adjacent FET groups affecting operational consistency
Solution Approach 1:
The device is divided into multiple independent FET groups (first FET group and second FET group) that are spatially separated by the source bus bar structure. Each FET group operates independently with its own heat dissipation path, preventing thermal coupling between groups while maintaining high overall device capacity.
Solution Approach 2:
The source bus bar serves as a thermal intermediary structure that physically separates the first and second FET groups. This intermediary element provides electrical connection while creating thermal isolation, allowing current to flow through multiple groups without direct heat transfer between them.
2Area of stationary object
If transistors are arranged in a compact configuration to reduce device area, then space utilization is improved, but heat dissipation becomes more difficult and heat interference increases
Solution Approach 1:
The source bus bar extends in the thickness direction (vertical dimension) of the substrate, creating a three-dimensional arrangement that separates FET groups vertically rather than only horizontally. This dimensional approach reduces the planar area required while providing effective thermal separation pathways in the vertical direction.
3Object-affected harmful factors
If via holes are added to the source bus bar for thermal isolation, then heat interference is reduced, but device complexity and manufacturing steps increase
Solution Approach 1:
The via holes in the source bus bar serve multiple functions simultaneously: they provide thermal isolation between FET groups, maintain mechanical structural integrity of the bus bar, and enable electrical connection pathways. This multi-functionality reduces the need for separate dedicated thermal isolation structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively suppresses heat interference between FET groups, maintaining consistent operation and reducing inductance and electromagnetic coupling, thereby enhancing high-frequency characteristics.
Implementation Method 1
a source bus bar provided on a first surface of a substrate and overlapping with a first via hole penetrating through the substrate as viewed from a thickness direction of the substrate
Data Source
AI summary
A semiconductor device includes a source bus bar provided on a first surface of a substrate and overlapping with a first via hole penetrating through the substrate, a plurality of first transistors arranged in a second direction intersecting a first direction, each of the first transistors including a first source finger, a first drain finger and a first gate finger which extend in the first direction on the first surface, the first source finger being electrically connected to the source bus bar, and a plurality of second transistors arranged in the second direction, each of the second transistors including a second source finger, a second drain finger and a second gate finger which extend in the first direction on the first surface, the second source finger being electrically connected to the source bus bar, the first transistors and the second transistors sandwiching the source bus bar.