Source-Down MOSFET Integration for Switched Mode Power Supply Efficiency
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Solution Overview
Problem
Switched mode power supply output stages face challenges in minimizing power losses due to switching events, particularly in high-power applications where cross-currents lead to prohibitively high power dissipation, and existing technologies do not effectively utilize monolithic integration to reduce parasitic inductance and gate-to-drain capacitance.
Innovation Solution
The integration of high-side and low-side MOSFET switches with monolithically integrated speed-up FETs on a single die, where the source is connected to the substrate, minimizing internal capacitance and parasitic inductance, and utilizing a common source configuration to enhance switching performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If vertical power MOSFETs with drain at back-side are used, then monolithic integration is enabled and parasitic inductance is reduced, but gate-to-drain capacitance remains high limiting switching speed
Solution Approach 1:
The patent inverts the conventional MOSFET structure by placing the source at the back-side of the die instead of the drain. This source-down configuration reverses the traditional architecture, enabling the source to be monolithically integrated with the gate driver while minimizing the gate-to-source capacitance path, thereby improving switching speed despite maintaining integration benefits.
Solution Approach 2:
The patent utilizes the third dimension (vertical depth of the die) by extending the source region to the back-side of the substrate. This dimensional approach allows the source connection to bypass traditional lateral routing paths, reducing parasitic inductance and capacitance through a direct vertical connection that exploits the depth dimension of the semiconductor structure.
2Loss of energy
If speed-up transistors are used to assist turn-off, then power losses during switching are reduced, but parasitic inductance in connections limits effectiveness
Solution Approach 1:
The patent merges the speed-up transistor and the main power MOSFET into a single monolithic device structure. The source-down configuration allows both transistors to share common source connections and substrate contacts, eliminating separate external connections and their associated parasitic inductances. This integration combines the functions of both transistors while minimizing the connection structure that would otherwise limit effectiveness.
3Ease of manufacture
If conventional MOSFET configuration is used, then manufacturing is straightforward, but cross-currents during simultaneous switching cause high power dissipation
Solution Approach 1:
The patent implements preliminary action by using the integrated speed-up transistor to pre-charge or pre-discharge the gate of the main power MOSFET before the main switching event. The source-down configuration enables this preliminary gate control action to occur more effectively by minimizing parasitic capacitances, ensuring that the main transistor switches cleanly without simultaneous conduction that would cause cross-currents and power dissipation.
Data Source
AI summary
An output stage for a switched mode power supply has a high-side switch having a first power FET and a first speed-up FET monolithically integrated onto a first die. A low-side switch has a second power FET and a second speed-up FET monolithically integrated onto a second die. A semiconductor device has the power FET and the speed-up FET monolithically integrated in a “source-down” configuration. A method of operating an output stage of a switched mode power supply alternately turns on and off a high-side and a low-side switch and drives at least one of the switches with a speed-up FET monolithically integrated with the switch.