FinFET Source/Drain Buffer Structure for Dopant Leakage Control
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Solution Overview
Problem
Dopants from the doped epitaxial material in fin-based transistors, such as nanostructure transistors, diffuse into the mesa region, leading to increased electron tunneling, short channel effects, and leakage, which degrade device performance.
Innovation Solution
Incorporating a buffer region under the source/drain region and a sidewall layer or dielectric region to prevent dopant migration, reducing short channel effects and leakage by forming an air gap between epitaxial layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If doped epitaxial material is used in source/drain regions, then device conductivity is improved, but dopants diffuse into the mesa region causing increased leakage and short channel effects
Solution Approach 1:
A buffer region comprising undoped or lightly-doped epitaxial material is introduced between the doped source/drain regions and the mesa region. This buffer region acts as an intermediary that prevents dopant diffusion into the mesa region while maintaining electrical connectivity, thereby eliminating the harmful dopant migration effect without sacrificing the conductivity benefit of doped regions.
2Object-generated harmful factors
If buffer region is introduced to prevent dopant migration, then leakage is reduced, but device structure becomes more complex
Solution Approach 1:
The source/drain region is segmented into multiple functional zones: a heavily-doped region for electrical contact, an undoped or lightly-doped buffer region for preventing dopant diffusion, and a transition region. This segmentation allows each zone to perform its specific function optimally while maintaining overall device performance and reducing leakage current.
3Manufacturing precision
If sidewall layer or dielectric region is added to block dopant migration, then short channel effects are reduced, but manufacturing process becomes more complex
Solution Approach 1:
A sidewall layer or dielectric region is introduced as an intermediary barrier between the doped source/drain regions and the mesa region. This lateral barrier prevents dopant migration along the sidewalls into the mesa region, providing three-dimensional dopant confinement. The sidewall layer can be formed through standard semiconductor fabrication processes such as atomic layer deposition (ALD) or chemical vapor deposition (CVD), making it compatible with existing manufacturing workflows.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The buffer region and sidewall layer/dielectric region effectively block dopant migration, enhancing device performance by decreasing off-current and leakage, and reducing short channel effects.
Implementation Method 1
Incorporating a buffer region under the source/drain region and a sidewall layer or dielectric region to prevent dopant migration
Implementation Method 2
reducing short channel effects and leakage by forming an air gap between epitaxial layers
Data Source
AI summary
Some implementations described herein provide techniques and semiconductor devices in which a buffer region is formed under a source/drain region of a device. The buffer region is configured to reduce, prevent, and/or block migration of dopants from the source/drain region to other areas of the device, such a mesa region of an adjacent fin structure. In some implementations, a sidewall layer is between the buffer region and the mesa region. Additionally, or alternatively, a dielectric region including a dielectric gas may be between the buffer region and the source/drain region.