Source/Drain Contact Liner for Gate Stack Etch Protection
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to maintain high-performance integrated circuits while minimizing contact resistance and energy consumption, which is often achieved through the use of metal silicide contacts, but these contacts face issues with scaling and reliability due to the need for precise and damage-resistant processing.
Innovation Solution
A method involving the formation of a dielectric spacer liner on the sidewalls of source/drain contacts to protect the gate stack during pre-amorphized implantation, using materials like silicon oxycarbide or silicon oxynitride, which prevents etchant damage and enhances the integrity of the metal semiconductor alloy contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal silicide contacts are used to reduce contact resistance and energy consumption, then circuit performance is improved, but the gate stack becomes vulnerable to damage during subsequent processing steps
Solution Approach 1:
A dielectric spacer liner is introduced as an intermediary protective layer between the metal silicide contact and the gate stack. This liner prevents direct contact between etchants used in contact hole formation and the gate stack, thereby protecting the gate stack from damage while allowing the metal silicide contact to maintain its low contact resistance property
Solution Approach 2:
The dielectric spacer liner is formed on the sidewalls of the source/drain contact before the contact hole etching process. This preliminary protective action ensures that the gate stack is protected in advance from potential etchant damage during subsequent processing steps
Data Source
AI summary
A device includes a gate structure, a source/drain structure, a source/drain conductor, a barrier layer, and a dielectric liner layer. The gate structure is over a semiconductor structure and includes a gate dielectric layer and at least one titanium-containing metal layer over the gate dielectric layer. The source/drain structure is adjacent the gate structure and a sidewall of the semiconductor structure. The source/drain conductor is over the source/drain structure. The barrier layer warps around the source/drain conductor. The dielectric liner layer is on a sidewall of the barrier layer. Both the dielectric liner layer and the barrier layer extend into the source/drain structure.