Semiconductor Source/Drain Layout to Limit Isolation Diffusion
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Solution Overview
Problem
Current semiconductor structures face challenges in improving the length of diffusion (LOD) effect and performance due to doping ions diffusing into isolation structures, leading to increased extension resistance and poor device performance, particularly in PMOS devices using embedded SiGe technology.
Innovation Solution
The semiconductor structure design includes a source/drain doped layer with a bulk layer whose side wall is spaced apart from the isolation structure, preventing doping ion diffusion and maintaining stress for improved carrier mobility, along with a cap layer and stress layer to enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source/drain bulk layer contacts the isolation structure, then the manufacturing process is simpler, but doping ions diffuse into the isolation structure causing increased extension resistance
Solution Approach 1:
A cap layer is introduced as an intermediary between the source/drain bulk layer and the isolation structure. This cap layer prevents doping ions from diffusing into the isolation structure while allowing the source/drain bulk layer to maintain its stress function, thereby reducing extension resistance without requiring direct spacing between the source/drain bulk layer and isolation structure.
Solution Approach 2:
The cap layer is formed on the source/drain bulk layer before the doping process. This preliminary action creates a protective barrier that prevents doping ion diffusion into the isolation structure during subsequent processing steps, addressing the extension resistance issue before it occurs.
2Reliability
If the source/drain bulk layer is positioned away from the isolation structure, then doping ion diffusion is prevented, but the device structure becomes more complex
Solution Approach 1:
The cap layer serves as a mediator that enables the source/drain bulk layer to be positioned closer to the isolation structure while still preventing doping ion diffusion. The cap layer fills the space between these components and provides the necessary barrier function, reducing structural complexity compared to requiring direct spacing.
Solution Approach 2:
The structure employs a composite arrangement with the cap layer made of a material suitable for preventing doping diffusion (such as silicon nitride or silicon oxide), combined with the source/drain bulk layer and isolation structure. This composite approach achieves effective diffusion control while maintaining a compact overall structure.
3Reliability
If stress material is applied to improve carrier mobility, then device performance improves, but the structure requires additional layers increasing complexity
Solution Approach 1:
The cap layer is designed to serve multiple functions: it prevents doping ion diffusion into the isolation structure, maintains the stress field in the channel area to improve carrier mobility, and provides a platform for subsequent processing steps. This multi-functionality reduces the need for separate dedicated stress layers, thereby reducing overall structural complexity.
Solution Approach 2:
The invention merges the diffusion prevention function and the stress maintenance function into a single integrated structure. The cap layer both prevents doping diffusion and maintains the stress field required for carrier mobility enhancement, combining what would traditionally require separate components into one unified element.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively reduces extension resistance and improves the LOD effect and overall performance of semiconductor structures by preventing doping ion diffusion and maintaining stress in the channel area.
Implementation Method 1
an embedded SiGe layer is formed in the source/drain area to introduce the compressive stress to the channel. This stress distorts the crystal lattice of the semiconductor, such that uniaxial stress is generated in the channel area
Implementation Method 2
This stress distorts the crystal lattice of the semiconductor, such that uniaxial stress is generated in the channel area, thereby affecting the band alignment and the charge transport performance of the semiconductor
Implementation Method 3
preventing doping ions in the source/drain bulk layer from diffusing into the isolation structure
Data Source
AI summary
A semiconductor structure and a forming method thereof are provided. The semiconductor structure includes: a substrate, including a device cell area and an isolated area located on a periphery of the device cell area; an isolation structure, located in the substrate of the isolated area; a device gate structure, located on the substrate of the device cell area; and a source/drain doped layer, embedded into the substrate of the device cell area on two sides of the device gate structure, the source/drain doped layer including a source/drain bulk layer, a side wall of the source/drain bulk layer located on an edge of the device cell area and the isolation structure being spaced apart.