Source Finger Layout for Low-Capacitance GaN HEMT Stability
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Solution Overview
Problem
In high-frequency transistors like GaN HEMT, increasing gain leads to potential oscillation and increased drain-source capacitance, which affects performance and efficiency.
Innovation Solution
A transistor design where selective connections are made between specific source electrodes, using wires and air bridges to suppress oscillation and capacitance, while maintaining high resonance frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source fingers are bundled by a source bus to suppress voltage current distribution and oscillation, then oscillation is suppressed, but drain-source capacitance increases due to parallel plate capacitor formation at intersection points
Solution Approach 1:
The source bus connection is segmented into two distinct groups: central source fingers are connected through the source bus to suppress oscillation, while outer source fingers are connected directly to the source pad without passing through the source bus. This segmentation prevents the formation of parallel plate capacitors at intersection points for the outer fingers, thereby reducing drain-source capacitance while maintaining oscillation suppression benefits from central finger connection.
Solution Approach 2:
Different connection methods are applied to different regions of the source fingers: central source fingers use source bus connection for oscillation suppression, while outer source fingers use direct source pad connection to minimize capacitance. This local differentiation optimizes the balance between oscillation suppression and capacitance reduction.
2Power
If gain is increased in high-frequency transistors to improve performance, then power-added efficiency improves, but oscillation occurs due to increased drain-source capacitance
Solution Approach 1:
The source finger connections are segmented into central and outer groups with different connection paths. Central fingers connect through the source bus to suppress oscillation, while outer fingers connect directly to the source pad to minimize capacitance formation. This enables higher gain operation without oscillation.
Solution Approach 2:
The outer source fingers are extracted from the source bus connection and connected directly to the source pad. This extraction removes the source of parallel plate capacitor formation at intersection points, reducing drain-source capacitance and enabling stable high-gain operation.
3Stability of the object's composition
If a source bus is used to connect all source fingers, then voltage current distribution is reduced, but the intersection with drain air bridges forms parallel plate capacitors that increase drain-source capacitance
Solution Approach 1:
The source finger connections are segmented into two groups: central source fingers maintain source bus connection for stable voltage current distribution, while outer source fingers use direct source pad connection to avoid capacitor formation. This segmentation preserves voltage distribution stability while reducing capacitance.
Solution Approach 2:
Outer source fingers are extracted from the source bus connection and connected directly to the source pad. This removes the harmful parallel plate capacitor intersections while the central fingers remain connected through the source bus to maintain voltage current distribution stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively suppresses oscillation and capacitance, maintaining high power-added efficiency and resonance frequency, thus enhancing transistor performance.
Implementation Method 1
A parallel plate capacitor is formed at a portion where the source bus and each of the drain air bridges intersect each other. Therefore, a drain-source capacitance of the high-frequency transistor may be increased.
Implementation Method 2
In the transistor according to the present disclosure, the first wire or the connection path is selectively provided at the portion strongly influencing on prevention of a standing wave. Therefore, it is possible to suppress the drain-source capacitance while suppressing oscillation.
Data Source
AI summary
A transistor according to the disclosure includes a semiconductor substrate, a source pad provided on an upper surface of the semiconductor substrate, a plurality of source electrodes provided on the upper surface of the semiconductor substrate and arranged in an arrangement direction, the plurality of source electrodes each including a first end connected to the source pad and a second end on a side opposite to the source pad, a plurality of drain electrodes arranged alternately with the plurality of source electrodes in the arrangement direction, a gate electrode and a first wire configured to connect the second ends of a plurality of central electrodes provided at a central part of the semiconductor substrate in the arrangement direction among the plurality of source electrodes, and not to connect the second ends of the source electrodes other than the plurality of central electrodes.