3D Semiconductor Memory Source-Gate Layout for Capacity Scaling
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in increasing data storage capacity and ensuring performance and reliability, particularly in three-dimensional memory cell arrangements.
Innovation Solution
A semiconductor memory device design featuring a peripheral circuit structure with a source layer and a stack structure of mold insulating films and gate electrodes, along with a channel structure intersecting these electrodes, enhances data storage capacity and reliability by optimizing the arrangement of memory cells in a three-dimensional manner.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in a two-dimensional manner, then the device structure is simple, but the data storage capacity is limited
Solution Approach 1:
The patent transitions from two-dimensional memory cell arrangement to three-dimensional arrangement by stacking multiple layers of memory cells vertically. This is achieved by forming alternating layers of first and second sacrificial materials, creating vertical channels that extend through multiple stacked layers, thereby significantly increasing storage capacity per unit area
Solution Approach 2:
The memory device is divided into multiple discrete layers with alternating sacrificial materials (first and second sacrificial materials) that are segmented and stacked vertically. Each layer can be independently processed and the segmented structure allows for systematic scaling of storage capacity by adding more layers
2Quantity of substance
If three-dimensional memory cell arrangement is implemented, then the data storage capacity increases, but the manufacturing precision requirements increase
Solution Approach 1:
Sacrificial materials (first and second sacrificial materials with different etch selectivities) are introduced as intermediary structures during manufacturing. These sacrificial layers serve as placeholders and alignment references that facilitate precise formation of vertical channels and gate electrodes, enabling accurate three-dimensional structure creation without direct high-precision alignment of final functional layers
Solution Approach 2:
The patent utilizes different etch selectivity parameters between first and second sacrificial materials to enable selective removal and precise formation of structures at different stages. By changing the material parameters (etch resistance, deposition properties) of alternating layers, the manufacturing process achieves high precision in three-dimensional structure formation
3Quantity of substance
If three-dimensional memory cell arrangement is implemented, then the data storage capacity increases, but the device reliability may deteriorate
Solution Approach 1:
The patent creates homogeneous structures by forming uniform alternating layers of first and second sacrificial materials throughout the three-dimensional stack. This homogeneity ensures consistent electrical properties and stress distribution across all layers, improving device reliability. The vertical channels and gate electrodes are formed with uniform dimensions and spacing, reducing variability in device performance
Data Source
AI summary
A semiconductor memory device comprises a peripheral circuit structure including a peripheral circuit substrate and a peripheral circuit element on the peripheral circuit substrate, a source layer including a first surface facing the peripheral circuit structure and a second surface opposite to the first surface, a stack structure including a plurality of mold insulating films and a plurality of gate electrodes alternately stacked on the first surface of the source layer, and a channel structure extending through the stack structure and contacting the source layer. The source layer is in contact with an uppermost gate electrode that is closest to the source layer among the plurality of gate electrodes.